Optimal Correlated Array Abstraction

1. A method, in a data processing system comprising a processor and a memory, for refining an abstraction of a netlist for verification or synthesis of an integrated circuit design, comprising: receiving, in the data processing system, an abstracted netlist corresponding to an original netlist of the integrated circuit design; determining, by the data processing system, elements, of an array of elements in the integrated circuit design, already present in the abstracted netlist; refining, by the data processing system, the abstracted netlist by expanding the abstracted netlist to include additional elements, of the array of elements, that are correlated with the elements already present in the abstracted netlist to thereby generate a refined abstracted netlist; and utilizing, by the data processing system, the refined abstracted netlist to perform at least one of verification or synthesis of the integrated circuit design, wherein the additional elements that are correlated with the elements already present in the abstracted netlist comprise additional elements, in the array of elements in the integrated circuit design, having a same row or column location in the array of elements as elements already present in the abstracted netlist.

2. The method of claim 1 , wherein the additional elements are additional gates selected based on a criteria of minimizing a total number of referenced columns and rows in the refined abstracted netlist.

3. The method of claim 1 , wherein refining the abstracted netlist further comprises eliminating portions of an array in the abstracted netlist that are not referenced during the verification or synthesis of the integrated circuit design.

4. The method of claim 1 , wherein refining the abstracted netlist comprises: deriving a set of candidate refinement gates as a set of cutpointed gates assigned a predetermined Boolean value in a spurious failure trace of the abstracted netlist; and identifying a subset of elements of the set of candidate refinement gates that correlates to array cells having a same row and same column as elements in the abstracted netlist.

5. The method of claim 4 , wherein refining the abstracted netlist further comprises: determining if the subset of elements of the set of candidate refinement gates is empty; and in response to the subset of elements of the set of candidate refinement gates being empty, selecting a criterion of either “same rows” or “same columns” for selection of a subset of elements from the candidate refinement gates having a characteristic corresponding to the selected criterion with regard to elements already present in the abstracted netlist.

6. The method of claim 1 , wherein refining the abstracted netlist further comprises: identifying rows of an array in the abstracted netlist that are not referenced during the verification or synthesis; and reducing address pins associated with the array in response to identifying rows in the array that are not referenced during the verification or synthesis.

7. The method of claim 6 , wherein identifying rows of an array in the abstracted netlist that are not referenced during the verification or synthesis comprises determining if no even numbered row in the array is referenced during the verification or synthesis, and wherein reducing address pins associated with the array comprises, in response to no even numbered row in the array being referenced during the verification or synthesis, dropping a least-significant address pin from the array.

8. The method of claim 6 , wherein reducing the address pins comprises: determining if a number of rows of the array referenced during the verification or synthesis is half or less of 2 to the power of the number of address pins of the array; and reducing a number of address pins by permuting an address space of the array to pack the remaining relevant rows by forming a bijection between the original rows of the array in the original netlist and post abstraction rows of the array.

9. The method of claim 1 , wherein refining the abstracted netlist comprises: deriving a set of candidate refinement gates; generating a new abstracted netlist having only non-array related gates from the abstracted netlist and the set of refinement gates; generating a set of gates representing a remainder of the abstracted netlist and the set of refinement gates that are not included in the new abstracted netlist; determining if a column of an array in the new abstracted netlist has no modeled cells in a set of array cells already included in the abstracted netlist or the set of candidate refinement gates; and replacing an array in the new abstracted netlist with an array that does not include the column having no modeled cells in the set of array cells already included in the abstracted netlist or the set of candidate refinement gates.

10. A computer program product comprising a computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed on a computing device, causes the computing device to: receive an abstracted netlist corresponding to an original netlist of an integrated circuit design; determine elements, of an array of elements in the integrated circuit design, already present in the abstracted netlist; refine the abstracted netlist by expanding the abstracted netlist to include additional elements, of the array of elements, that are correlated with the elements already present in the abstracted netlist to thereby generate a refined abstracted netlist; and utilize the refined abstracted netlist to perform at least one of verification or synthesis of the integrated circuit design, wherein the additional elements that are correlated with the elements already present in the abstracted netlist comprise additional elements, in the array of elements in the integrated circuit design, having a same row or column location in the array of elements as elements already present in the abstracted netlist.

11. The computer program product of claim 10 , wherein the additional elements are additional gates selected based on a criteria of minimizing a total number of referenced columns and rows in the refined abstracted netlist.

12. The computer program product of claim 10 , wherein refining the abstracted netlist further comprises eliminating portions of an array in the abstracted netlist that are not referenced during the verification or synthesis of the integrated circuit design.

13. The computer program product of claim 10 , wherein refining the abstracted netlist comprises: deriving a set of candidate refinement gates as a set of cutpointed gates assigned a predetermined Boolean value in a spurious failure trace of the abstracted netlist; and identifying a subset of elements of the set of candidate refinement gates that correlates to array cells having a same row and same column as elements in the abstracted netlist.

14. The computer program product of claim 13 , wherein refining the abstracted netlist further comprises: determining if the subset of elements of the set of candidate refinement gates is empty; and in response to the subset of elements of the set of candidate refinement gates being empty, selecting a criterion of either “same rows” or “same columns” for selection of a subset of elements from the candidate refinement gates having a characteristic corresponding to the selected criterion with regard to elements already present in the abstracted netlist.

15. The computer program product of claim 10 , wherein refining the abstracted netlist further comprises: identifying rows of an array in the abstracted netlist that are not referenced during the verification or synthesis; and reducing address pins associated with the array in response to identifying rows in the array that are not referenced during the verification or synthesis.

16. The computer program product of claim 15 , wherein identifying rows of an array in the abstracted netlist that are not referenced during the verification or synthesis comprises determining if no even numbered row in the array is referenced during the verification or synthesis, and wherein reducing address pins associated with the array comprises, in response to no even numbered row in the array being referenced during the verification or synthesis, dropping a least-significant address pin from the array.

17. The computer program product of claim 15 , wherein reducing the address pins comprises: determining if a number of rows of the array referenced during the verification or synthesis is half or less of 2 to the power of the number of address pins of the array; and reducing a number of address pins by permuting an address space of the array to pack the remaining relevant rows by forming a bijection between the original rows of the array in the original netlist and post abstraction rows of the array.

18. The computer program product of claim 10 , wherein refining the abstracted netlist comprises: deriving a set of candidate refinement gates; generating a new abstracted netlist having only non-array related gates from the abstracted netlist and the set of refinement gates; generating a set of gates representing a remainder of the abstracted netlist and the set of refinement gates that, are not included in the new abstracted netlist; determining if a column of an array in the new abstracted netlist has no modeled cells in a set of array cells already included in the abstracted netlist or the set of candidate refinement gates; and replacing an array in the new abstracted netlist with an array that does not include the column having no modeled cells in the set of array cells already included in the abstracted netlist or the set of candidate refinement gates.

19. An apparatus, comprising: a processor; and a memory coupled to the processor, wherein the memory comprises instructions which, when executed by the processor, cause the processor to: receive an abstracted netlist corresponding to an original netlist of an integrated circuit design; determine elements, of an array of elements in the integrated circuit design, already present in the abstracted netlist; refine the abstracted netlist by expanding the abstracted netlist to include additional elements, of the array of elements, that are correlated with the elements already present in the abstracted netlist to thereby generate a refined abstracted netlist; and utilize the refined abstracted netlist to perform at least one of verification or synthesis of the integrated circuit design, wherein the additional elements that are correlated with the elements already present in the abstracted netlist comprise additional elements, in the array of elements in the integrated circuit design, having a same row or column location in the array of elements as elements already present in the abstracted netlist.

20. The apparatus of claim 19 , wherein the additional elements are additional gates selected based on a criteria of minimizing a total number of referenced columns and rows in the refined abstracted netlist.

21. The apparatus of claim 19 , wherein refining the abstracted netlist further comprises eliminating portions of an array in the abstracted netlist that are not referenced during the verification or synthesis of the integrated circuit design.

22. The apparatus of claim 19 , wherein refining the abstracted netlist comprises: deriving a set of candidate refinement gates as a set of cutpointed gates assigned a predetermined Boolean value, in a spurious failure trace of the abstracted netlist; identifying a subset of elements of the set of candidate refinement gates that correlates to array cells having a same row and same column as elements in the abstracted netlist; determining if the subset of elements of the set of candidate refinement gates is empty; and in response to the subset of elements of the set of candidate refinement gates being empty, selecting a criterion of either “same rows” or “same columns” for selection of a subset of elements from the candidate refinement gates having a characteristic corresponding to the selected criterion with regard to elements already present in the abstracted netlist.