Processor Architecture for Multipass Processing of Instructions Downstream of a Stalled Instruction

1. A method, comprising: switching operation of a processor from a general execution mode to an advance execution mode in response to a first cache miss of an instruction during performance in the general execution mode, the first cache miss resulting in a first stall lasting for a first amount of time; during the advance execution mode, performing multiple speculative execution passes through several instructions subsequent to the instruction causing the first cache miss with the processor, and storing results from one or more of the speculative execution passes; during performance of a first one of the speculative execution passes, executing a subsequent one of the instructions that causes a second cache miss resulting in a second stall that lasts a second amount of time; performing a second one of the speculative execution passes to process the subsequent one of the instructions after the second amount of time has lapsed; applying a subsequent one of the results from the subsequent one of the instructions to perform one or more other instructions during the speculative execution passes before the first amount of time has lapsed; and returning to the general execution mode and applying the results to reduce execution time for the several instructions subsequent to the instruction causing the first cache miss.

2. The method of claim 1 , which includes merging the results; and after the merging, returning the processor to the general execution mode.

3. The method of claim 1 , which includes the processor defining a pipeline instruction handling architecture including a general execution cache, an advance execution cache, a nominal register file, and a speculative register file.

4. The method of claim 1 , which includes: maintaining memory access order during the advance execution mode with a speculative memory address queue; and instruction regrouping based on the results from the advance execution mode.

5. A method, comprising: operating a processor in a general execution mode; with the processor, performing a first advance execution processing pass through a sequence of instructions in response to a stall of one of the instructions in the general execution mode, the stall lasting for a first amount of time; during performance of the first advance execution processing pass, executing a subsequent one of the instructions in the sequence that stalls a second amount of time; performing a second advance execution processing pass through the sequence in which the subsequent one of the instructions is processed after the second amount of time has lapsed; and applying a valid result from the subsequent one of the instructions to perform one or more other instructions in the sequence during the second advance execution processing pass before the first amount of time has lapsed.

6. The method of claim 5 , which includes the processor defining a pipeline instruction handling architecture including a first cache accessed during performance of the general execution mode and a second cache accessed during performance of the advance execution processing pass.

7. The method of claim 6 , wherein the architecture defines a nominal execution register file and a speculative execution register file.

8. The method of claim 5 , which includes: performing the first pass and the second pass during an advance mode of execution of the processor; performing processor instruction regrouping; merging instruction results; and returning to the general execution mode.

9. The method of claim 5 , wherein the performing of the first pass and the second pass occurs while the processor operates in an advance execution mode and further comprising: switching to a rallying mode of processor execution from the advance execution mode; and returning to the general execution mode from the rallying mode.

10. An apparatus, comprising: processor instruction execution architecture including: an instruction processing pipeline with an instruction buffer; a nominal register file coupled to the pipeline; a speculative execution register file coupled to the pipeline; a cache; and operating logic to process instructions in the instruction buffer with the pipeline, the operating logic being structured to switch from a nominal processing mode that accesses the nominal register file to a speculative processing mode that accesses the speculative execution register file in response to a first cache miss resulting in a first stall that lasts for a first amount of time by an instruction accessing the cache, and during the speculative processing mode to: perform a first speculative execution pass through a sequence of instructions including executing a subsequent one of the instructions in the sequence that results in a second cache miss resulting in a second stall that lasts a second amount of time, perform a second speculative execution pass through the sequence of instructions in which the subsequent one of the instructions in the sequence is processed after the second amount of time has lapsed, apply a subsequent result from the subsequent one of the instructions in the sequence to perform one or more other instructions in the sequence during the second speculative execution pass before the first amount of time has lapsed, and store results from the speculative processing mode, and the operating logic being further structured to return to the nominal processing mode and use the results to decrease execution time for the sequence of instructions.

11. The apparatus of claim 10 , wherein the architecture includes: a speculative mode cache, wherein the operating logic is structured to access the speculative mode cache during performance of the speculative processing mode; and a speculative memory address queue to maintain memory access order.

12. The apparatus of claim 10 , wherein the architecture includes means for redirecting access from the nominal register file to the speculative execution register file and means for instruction regrouping in accordance with the results.

13. The apparatus of claim 10 , wherein the architecture includes a bit vector to mark one or more of the sequence instructions subject to the speculative processing mode.

14. The apparatus of claim 10 , further comprising a computer with a processor including the architecture.