Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for implementing serial link training sequences for training a serial link in an interconnect system, said method comprising: providing a transmit device with the serial link for transmitting data; providing a receiver device with the serial link for receiving data; said transmit device, transmitting a training sequence (TS) pattern; said transmit device, transmitting random data for a predefined time duration; said transmit device, repeating the steps of transmitting the TS-pattern, and transmitting the random data for the predefined time duration; said receiver device performing receiver initialization steps, said transmit device, advancing to a next TS-pattern when said receiver device detects a current TS-pattern and said receiver device being ready for initialization to advance; and said transmit device, repeating the steps of transmitting the next TS-pattern, and transmitting the random data for the predefined time duration, said receiver device performing receiver initialization steps.
2. The method for implementing serial link training sequences as recited in claim 1 wherein providing a transmit device includes providing a transmit Linear Feedback Shift Register (LFSR) with the serial link for transmitting data, said transmit Linear Feedback Shift Register (LFSR) transmitting the random data for the predefined time duration; and wherein said transmit device and said receiver device continue with said transmit device, advancing to a next TS-pattern when said receiver device detects a current TS-pattern and said receiver device being ready for initialization to advance; and said transmit device, repeating the steps of transmitting the next TS-pattern, and transmitting the random data for the predefined time duration, said receiver device performing receiver initialization steps until a final TS-pattern is transmitted.
3. The method for implementing serial link training sequences as recited in claim 1 wherein providing a receiver device includes providing said receiver device for receiving the transmitted TS-pattern and the transmitted random data.
4. The method for implementing serial link training sequences as recited in claim 1 wherein transmitting random data for a predefined time duration includes providing said predefined time duration of the transmitted random data substantially greater than a time interval of each transmitted TS-pattern.
5. The method for implementing serial link training sequences as recited in claim 1 wherein transmitting random data for a predefined time duration includes providing said predefined time duration of the transmitted random data approximately equal to ten times a time interval of each transmitted TS-pattern.
6. The method for implementing serial link training sequences as recited in claim 1 wherein transmitting random data for a predefined time duration includes providing a periodicity for random data generation greater than an overall time interval for performing the serial link training sequences.
7. The method for implementing serial link training sequences as recited in claim 1 wherein said receiver device detects a plurality of the training sequence (TS) patterns separated by the predefined time interval.
8. The method for implementing serial link training sequences as recited in claim 1 wherein said receiver device detects a plurality of the training sequence (TS) patterns separated by the predefined time interval, and said receiver device performing receiver initialization steps.
9. The method for implementing serial link training sequences as recited in claim 1 wherein said receiver device detects a plurality of the training sequence (TS) patterns separated by the predefined time interval and performs a plurality of receiver initialization steps including acquiring byte lock.
10. A circuit for implementing serial link training sequences for training a serial link in an interconnect system comprising: a link interface coupled to the serial link, said link interface including a transmit device coupled to the serial link for transmitting data and a receiver device coupled to the serial link for receiving data; said transmit device, transmitting a training sequence (TS) pattern; said transmit device, transmitting random data for a predefined time duration; said transmit device, repeating the steps of transmitting the TS-pattern, and transmitting the random data for the predefined time duration; said receiver device performing receiver initialization steps, said transmit device, advancing to a next TS-pattern when said receiver device detects a current TS-pattern and said receiver device being ready for initialization to advance; and said transmit device, repeating the steps of transmitting the next TS-pattern, and transmitting the random data for the predefined time duration, said receiver device performing receiver initialization steps.
11. The circuit for implementing serial link training sequences as recited in claim 10 wherein said receiver device detects a plurality of the training sequence (TS) patterns separated by the predefined time interval.
12. The circuit for implementing serial link training sequences as recited in claim 11 wherein said receiver device performs a plurality of receiver initialization steps including acquiring byte lock; and wherein said transmit device and said receiver device continue with said transmit device, advancing to a next TS-pattern when said receiver device detects a current TS-pattern and said receiver device being ready for initialization to advance; and said transmit device, repeating the steps of transmitting the next TS-pattern, and transmitting the random data for the predefined time duration, said receiver device performing receiver initialization steps until a final TS-pattern is transmitted.
13. The circuit for implementing serial link training sequences as recited in claim 11 wherein said transmit device includes a transmit Linear Feedback Shift Register (LFSR) coupled to the serial link for transmitting data, said transmit Linear Feedback Shift Register (LFSR) transmitting the random data for the predefined time duration.
14. The circuit for implementing serial link training sequences as recited in claim 11 wherein said predefined time duration of the transmitted random data is substantially greater than a time interval of each transmitted TS-pattern.
15. The circuit for implementing serial link training sequences as recited in claim 11 wherein said transmit device transmitting random data includes said transmit device providing a periodicity for random data generation greater than an overall time interval for performing the serial link training sequences.
16. A multiple-path local rack interconnect system comprising: a plurality of interconnect chips; a plurality of serial links connected between each of said plurality of interconnect chips; each of said interconnect chips including a link interface for implementing serial link training sequences, said link interface coupled to the serial link, said link interface including a transmit device coupled to the serial link for transmitting data and a receiver device coupled to the serial link for receiving data; said transmit device, transmitting a training sequence (TS) pattern; said transmit device, transmitting random data for a predefined time duration; and said transmit device, repeating the steps of transmitting the TS-pattern, and transmitting the random data for the predefined time duration, said receiver device performing receiver initialization steps, said transmit device, advancing to a next TS-pattern when said receiver device detects a current TS-pattern and said receiver device being ready for initialization to advance; and said transmit device, repeating the steps of transmitting the next TS-pattern, and transmitting the random data for the predefined time duration, said receiver device performing receiver initialization steps.
17. The multiple-path local rack interconnect system as recited in claim 16 wherein said transmit device of said link interface includes a transmit Linear Feedback Shift Register (LFSR) coupled to the serial link for transmitting data, said transmit Linear Feedback Shift Register (LFSR) transmitting the random data for the predefined time duration and wherein said transmit device and said receiver device continue with said transmit device, advancing to a next TS-pattern when said receiver device detects a current TS-pattern and said receiver device being ready for initialization to advance; and said transmit device, repeating the steps of transmitting the next TS-pattern, and transmitting the random data for the predefined time duration, said receiver device performing receiver initialization steps until a final TS-pattern is transmitted.
18. The multiple-path local rack interconnect system as recited in claim 16 wherein said receiver device of said link interface includes a receive Linear Feedback Shift Register (LFSR) coupled to the serial link for receiving data; said receiver device detects a plurality of the training sequence (TS) patterns separated by the predefined time interval, and said receiver device performs a plurality of receiver initialization steps including acquiring byte lock.
19. The multiple-path local rack interconnect system as recited in claim 16 wherein said predefined time duration of the transmitted random data is substantially greater than a time interval of each transmitted TS-pattern.
20. A design structure embodied in a machine readable medium used in a design process, the design structure comprising: a circuit tangibly embodied in the machine readable medium used in the design process, said circuit for implementing serial link training sequences for training a serial link, said circuit comprising: a link interface coupled to the serial link, said link interface including a transmit device coupled to the serial link for transmitting data and a receiver device coupled to the serial link for receiving data; said transmit device, transmitting a training sequence (TS) pattern; said transmit device, transmitting random data for a predefined time duration; and said transmit device, repeating the steps of transmitting the TS-pattern, and transmitting the random data for the predefined time duration, said receiver device performing receiver initialization steps, said transmit device, advancing to a next TS-pattern when said receiver device detects a current TS-pattern and said receiver device being ready for initialization to advance; and said transmit device, repeating the steps of transmitting the next TS-pattern, and transmitting the random data for the predefined time duration, said receiver device performing receiver initialization steps, wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said circuit.
21. The design structure of claim 20 , wherein the design structure comprises a netlist, which describes said circuit.
22. The design structure of claim 20 , wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.
23. The design structure of claim 20 , wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.
24. The design structure of claim 20 , wherein said transmit device and said receiver device continue with said transmit device, advancing to a next TS-pattern when said receiver device detects a current TS-pattern and said receiver device being ready for initialization to advance; and said transmit device, repeating the steps of transmitting the next TS-pattern, and transmitting the random data for the predefined time duration, said receiver device performing receiver initialization steps until a final TS-pattern is transmitted; and wherein said receiver device detects a plurality of the training sequence (TS) patterns separated by the predefined time interval and performs a plurality of receiver initialization steps including acquiring byte lock.
Unknown
September 25, 2012
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