Memory and Operating Method Thereof

1. A method of programming data in a memory, the memory comprising a plurality of manufacture-defined blocks, a plurality of user-defined blocks and an information block, the method comprising steps of: obtaining a programming address pointing to a user-defined block in the memory and programming data; determining whether the user-defined block is already programmed and cannot be erased; and if the user-defined block is already programmed and cannot be erased, searching an empty manufacture-defined block among the manufacture-defined blocks, storing the programming address and a replacing address pointing to the empty manufacture-defined block to an information block, and storing the programming data to the empty manufacture-defined block, wherein, the manufacture-defined block is implemented with one of a replacing cell row and a replacing cell column, and the manufacture-defined block and the user-defined block have a same matrix size; and the manufacture-defined blocks and the user-defined blocks are implemented with one time programmable (OTP) memory blocks.

2. The method according to claim 1 , further comprising step of: storing the programming data to the user-defined block if the user-defined block is not programmed.

3. A method of reading data stored in a memory, the memory comprising an information block, a user-defined block and a manufacture-defined block, the method comprising steps of: obtaining a read address; reading the information block in the memory to obtain a programming address, which points to the user-defined block, and a replacing address, wherein the user-defined block pointed by the programming address in the information block is already programmed and cannot be erased; determining whether the read address corresponds to the programming address; and reading the manufacture-defined block to obtain the data corresponding to the read address if the read address corresponds to the programming address, wherein, the manufacture-defined block is implemented with one of a replacing cell row and a replacing cell column, and the manufacture-defined block and the user-defined block have a same matrix size; and the manufacture-defined blocks and the user-defined blocks are implemented with one time programmable (OTP) memory blocks.

4. The method according to claim 3 , further comprising step of: reading the user-defined block to obtain the data if the read address does not correspond to the replacing address.

5. A memory, comprising: a memory array, comprising a manufacture-defined block, an information block, and a user-defined block; and a logic circuit, for receiving a programming address pointing to the user-defined block and programming data, determining whether the user-defined block is already programmed, and when the user-defined block is already programmed, providing a replacing address pointing to the manufacture-defined block for storing the programming data, wherein, the manufacture-defined block is implemented with one of a replacing cell row and a replacing cell column, and the manufacturer-defined block and the user-defined block have a same matrix size.

6. The memory according to claim 5 , wherein the logic circuit further stores the program address and the replacing address in the information block indicating the user-defined block is replaced.

7. The memory according to claim 5 , wherein: when the logic circuit receives a read address pointing to the user-defined block, the logic circuit determines whether the user-defined block is replaced according to the program address and the replacing address in the information block or not; and the logic circuit reads the manufacture-defined block to obtain the programming data according to the replacing address.

8. The memory according to claim 5 , wherein each memory cell of the memory array is a metal oxide semiconductor (MOS) transistor.

9. The memory according to claim 5 , wherein each memory cell of the memory array is a diode device.

10. The memory according to claim 5 , wherein each memory cell of the memory array is a fuse device.