Data Procssing System with Peripheral Configuration Information Error Detection

1. In a data processing system including a first master operably coupled to a peripheral bus interface and a plurality of peripherals operably coupled to the peripheral bus interface, wherein the first master communicates with each of the plurality of peripherals via the peripheral bus interface, a method comprising: initiating a write, by the first master, of configuration information to a first peripheral of the plurality of peripherals; in response to initiating the write, providing the configuration information via the peripheral bus interface for storage into the first peripheral, wherein a first error syndrome of the configuration information is generated by the peripheral bus interface; storing the configuration information in a first storage location of the first peripheral; storing the first error syndrome in storage circuitry of the peripheral bus interface; reading the configuration information from the first storage location after the storing the configuration information; generating by the peripheral bus interface a second error syndrome of the configuration information read from the first storage location from the reading the configuration information; comparing the first error syndrome with the second error syndrome to determine if an error exists in the configuration information read from the first storage location; wherein the first master initiates the write of the configuration information stored in the first peripheral in accordance with a first memory mapping of the plurality of peripherals, and the reading of the configuration information stored in the first peripheral is initiated in accordance with a second memory mapping of the plurality of peripherals, different from the first memory mapping.

2. The method of claim 1 , wherein the reading, the generating, and the comparing are performed periodically to determine if an error exists in the configuration information from the first storage location.

3. In a data processing system including a first master operably coupled to a peripheral bus interface and a plurality of peripherals operably coupled to the peripheral bus interface, wherein the first master communicates with each of the plurality of peripherals via the peripheral bus interface, a method comprising: initiating a write, by the first master, of configuration information to a first peripheral of the plurality of peripherals; in response to initiating the write, providing the configuration information via the peripheral bus interface for storage into the first peripheral, wherein a first error syndrome of the configuration information is generated by the peripheral bus interface; storing the configuration information in a first storage location of the first peripheral storing the first error syndrome in storage circuitry of the peripheral bus interface; reading the configuration information from the first storage location after the storing the configuration information; generating by the peripheral bus interface a second error syndrome of the configuration information read from the first storage location from the reading the configuration information; comparing the first error syndrome with the second error syndrome to determine if an error exists in the configuration information read from the first storage location; initiating a read of the configuration information stored in the first storage location wherein the reading is performed in response to the initiating a read; determining if error detection is to be performed for the read; wherein the generating and the comparing is performed if the determining determines that error detection is to be performed for the read; wherein the determining is based on which entity within the data processing system initiated the read of the configuration information stored in the first storage location.

4. The method of claim 3 , wherein when the entity comprises the first master, the method further comprises determining that the comparing is not to be performed.

5. The method of claim 3 , wherein when the entity comprises the peripheral bus interface, the method further comprises determining that error detection is to be performed.

6. The method of claim 3 , wherein the data processing system further comprises a second master, wherein the second master is operably coupled to the peripheral bus interface and communicates with each of the peripherals via the peripheral bus interface, and wherein when the entity comprises the second master, the method further comprises determining that error detection is to be performed.

7. The method of claim 3 , wherein the reading, the generating, and the comparing are performed periodically to determine if an error exists in the configuration information from the first storage location.

8. In a data processing system including a first master operably coupled to a peripheral bus interface and a plurality of peripherals operably coupled to the peripheral bus interface, wherein the first master communicates with each of the plurality of peripherals via the peripheral bus interface, a method comprising: initiating a write, by the first master, of configuration information to a first peripheral of the plurality of peripherals; in response to initiating the write, providing the configuration information via the peripheral bus interface for storage into the first peripheral, wherein a first error syndrome of the configuration information is generated by the peripheral bus interface; storing the configuration information in a first storage location of the first peripheral storing the first error syndrome in storage circuitry of the peripheral bus interface; reading the configuration information from the first storage location after the storing the configuration information; generating by the peripheral bus interface a second error syndrome of the configuration information read from the first storage location from the reading the configuration information; comparing the first error syndrome with the second error syndrome to determine if an error exists in the configuration information read from the first storage location; initiating a read of the configuration information stored in the first storage location and determining if error detection is to be performed for the read; wherein the generating and the comparing is performed if the determining determines that error detection is to be performed for the read; wherein the determining if error detection is to be performed for the read is based on which memory map of the peripherals is used to initiate the read of the configuration information.

9. The method of claim 8 , wherein when a first memory map of the peripherals is used to initiate the read, the method further comprises determining that error detection is not to be performed, and when a mirrored memory map of the peripherals is used to initiate the read, the method further comprises determining that error detection is to be performed.

10. The method of claim 8 , wherein the reading, the generating, and the comparing are performed periodically to determine if an error exists in the configuration information from the first storage location.

11. In a data processing system including a first master operably coupled to a peripheral bus interface and a plurality of peripherals operably coupled to the peripheral bus interface, wherein the first master communicates with each of the plurality of peripherals via the peripheral bus interface, a method comprising: providing configuration information via the peripheral bus interface for storage into a first peripheral of the plurality of peripherals, wherein a first error syndrome of the configuration information is generated by the peripheral bus interface; storing the configuration information provided via the peripheral bus interface in the first peripheral; storing the first error syndrome in storage circuitry of the peripheral bus interface; initiating a read of the configuration information stored in the first peripheral after the storing of the configuration information; and in response to the initiating the read, receiving the configuration information from the first peripheral, wherein a second error syndrome of the configuration information received from the first peripheral is generated by the peripheral bus interface and compared to the first error syndrome to determine if an error exists in the configuration information received from the first peripheral; initiating, by the first master, a write of the configuration information to the first peripheral, wherein the providing the configuration information is performed in response to the initiating the write; wherein the initiating the read of the configuration information stored in the first peripheral is performed by the peripheral bus interface; wherein the first master initiates the write of the configuration information stored in the first peripheral in accordance with a first memory mapping of the plurality of peripherals, and the peripheral bus interface initiates the read of the configuration information stored in the first peripheral in accordance with a second memory mapping of the plurality of peripherals, different from the first memory mapping.

12. The method of claim 11 , further comprising: providing second configuration information via the peripheral bus interface for storage into a second peripheral of the plurality of peripherals, wherein a third error syndrome of the second configuration information is generated by the peripheral bus interface; storing the second configuration information provided via the peripheral bus interface in the second peripheral; storing the third error syndrome in the storage circuitry of the peripheral bus interface; initiating a read of the second configuration information stored in the second peripheral after the storing the second configuration information; and in response to the initiating the read of the second configuration information, receiving the second configuration information from the second peripheral, wherein a fourth error syndrome of the second configuration information received from the second peripheral is generated by the peripheral bus interface and compared to the third error syndrome to determine if an error exists in the second configuration information received from the second peripheral.

13. The method of claim 11 , further comprising: initiating, by the first master, a write of the configuration information to the first peripheral, wherein the providing the configuration information is performed in response to the initiating the write.

14. The method of claim 11 wherein the initiating a read of the configuration information stored in the first peripheral and the receiving, in response to the initiating the read, are performed periodically to determine if an error exists in the configuration information received from the first peripheral.

15. In a data processing system including a first master operably coupled to a peripheral bus interface and a plurality of peripherals operably coupled to the peripheral bus interface, wherein the first master communicates with each of the plurality of peripherals via the peripheral bus interface, a method comprising: providing configuration information via the peripheral bus interface for storage into a first peripheral of the plurality of peripherals, wherein a first error syndrome of the configuration information is generated by the peripheral bus interface; storing the configuration information provided via the peripheral bus interface in the first peripheral; storing the first error syndrome in storage circuitry of the peripheral bus interface; initiating a read of the configuration information stored in the first peripheral after the storing of the configuration information; and in response to the initiating the read, receiving the configuration information from the first peripheral, wherein a second error syndrome of the configuration information received from the first peripheral is generated by the peripheral bus interface and compared to the first error syndrome to determine if an error exists in the configuration information received from the first peripheral; initiating, by the first master, a write of the configuration information to the first peripheral, wherein the providing the configuration information is performed in response to the initiating the write; wherein the data processing system further comprises a second master operably coupled to the peripheral bus interface and communicates with each of the peripherals via the peripheral bus interface, and wherein the initiating the read of the configuration information stored in the first peripheral is performed by the second master.

16. The method of claim 15 , further comprising: initiating a second read by the first master of the configuration information stored in the first peripheral; in response to the initiating the second read by the first master, receiving the configuration information from the first peripheral via the peripheral bus interface, wherein the peripheral bus interface does not perform error detection on the configuration information received from the first peripheral; and providing the configuration information received from the first peripheral to the first master.

17. The method of claim 15 further comprising: initiating a second read by the first master of the configuration information stored in the first peripheral; in response to the initiating the second read by the first master, receiving the configuration information from the first peripheral via the peripheral bus interface; wherein the first master initiates the second read of the configuration information stored in the first peripheral in accordance with a first memory mapping of the plurality of peripherals, and a second master initiates the read of the configuration information stored in the first peripheral in accordance with a second memory mapping of the plurality of peripherals, different from the first memory mapping.

18. The method of claim 15 wherein the initiating a read of the configuration information stored in the first peripheral and the receiving, in response to the initiating the read, are performed periodically to determine if an error exists in the configuration information received from the first peripheral.

19. A data processing system, comprising: a first master; a peripheral bus interface, wherein the first master is operably coupled to the peripheral bus interface; and a plurality of peripherals operably coupled to the peripheral bus interface, wherein the first master communicates with each of the plurality of peripherals via the peripheral bus interface, and wherein: the first master initiates storage of configuration information into each of the plurality of peripherals, wherein when the configuration information is provided for storage into each of the plurality of peripherals, an error syndrome for the configuration information for each of the plurality of peripherals is generated by the peripheral bus interface and stored in storage circuitry of the peripheral bus interface; for error detection of configuration information, when configuration information stored in a peripheral of the plurality of peripherals is read from the peripheral and is received in the peripheral bus interface, the peripheral bus interface generates an error syndrome of the configuration information received from the peripheral and compares the error syndrome to an error syndrome generated during a write of the configuration information to the peripheral to determine if an error exists in the configuration information received from a peripheral; a first memory mapping of the plurality of peripherals is used by the first master to initiate the storage of configuration information to the plurality of peripherals and a mirrored memory mapping, different from the first memory mapping, of the plurality of peripherals is used to initiate reads of configuration information stored in the plurality of peripherals for error detection.

20. The data processing system of claim 19 , wherein the peripheral bus interface initiates the read of the configuration information stored in the peripheral for error detection.

21. The data processing system of claim 17 , wherein the peripheral bus interface initiates periodically the read of the configuration information stored in the peripheral for error detection.