Method and Apparatus for Versatile Controllability and Observability in Prototype System

1. A prototyping system for verifying and debugging an integrated circuit design under verification (DUV) comprising: a host workstation comprising a processor and a first memory, the host workstation configured to provide a plurality of configured Field Programmable Gate Array (FPGA) images and runtime control information, wherein each of the plurality of FPGA images is downloaded to a respective FPGA device, of a of FPGA devices, and each of the plurality of FPGA images contains a portion of the DUV, and a respective verification module, of a plurality of verification modules, wherein each of the plurality of verification modules is associated with a respective FPGA device; and an interface configured to provide timing and control information to each of the plurality of verification modules based on the runtime control information received from the host workstation, the interface comprising a controller and a second memory, the second memory being configured to store probed signal values associated with a first portion of the DUV received from a first verification module, of the of verification modules, and the controller being configured to process the probed signal values, wherein the first verification module is coupled with the interface and configured to control and probe the signal values of the first portion of the DUV in response to the timing and control information received from the interface, wherein the first portion of the DUV corresponds to a first FPGA device of the plurality of FPGA devices.

2. The system of claim 1 , wherein the interface is further configured to send commands for reconfiguring a first configured FPGA image, of the plurality of FPGA images, in response to a request from the host workstation.

3. The system of claim 1 , wherein the controller in the interface is configured to create a trigger condition based at least in part on the runtime control information received from the host workstation.

4. The system of claim 3 , wherein the trigger condition is based at least in part on timing information received from the host workstation.

5. The system of claim 1 , wherein the first verification module is configured to probe a predetermined signal in response to at least the control information received from the interface.

6. The system of claim 1 , wherein the controller in the interface is further configured to provide a clock signal and a reset signal to at least the first verification module.

7. The system of claim 1 , wherein the first verification module comprises: a first circuit configured to connect to and probe predetermined signals located within the first portion of the DUV; and a second circuit configured to perform at least one of decoding and encoding data exchanged with the interface.

8. The system of claim 7 , wherein the predetermined signals are based in part on register transfer language (RTL) information included in a design database in the host workstation.

9. The system of claim 1 , wherein the processing comprises decoding the received probed signal values.

10. A method comprising: receiving, at an interface, from a host workstation, a plurality of configured Field Programmable Gate Array FPGA images and runtime control information, wherein each of the plurality of FPGA images contains a respective portion of an integrated circuit design under verification (DUV), and a respective verification module, of a plurality of verification modules, wherein each of the plurality of verification modules is associated with a respective FPGA device of a plurality of FPGA devices, and each of the FPGA images is downloaded to a respective FPGA device, of a plurality of FPGA devices; sending, by the interface, each of the received plurality of configured FPGA images to each of the respective FPGA devices; sending, by the interface, timing and control information to each of the respective verification modules, of the plurality of verification modules, based on the runtime control information received from the host workstation; controlling, by each of the respective verification modules, the respective portion of the DUV in each of the respective FPGA devices in response to the timing and control information received from the interface; receiving, by the interface, from a first verification module of the plurality of verification modules, probed signal values associated with a first portion of the DUV; and processing and storing in a memory within the interface, by a controller in the interface, at least a portion of the probed signal values received from the first verification module.

11. The method of claim 10 , further comprising: creating, by the interface, a trigger condition based on the runtime control information received from the host workstation, wherein the first verification module captures a probed signal value associated with a predetermined signal associated with the first portion of the DUV.

12. The method of claim 11 , wherein the trigger condition is based in part on timing information received from the host workstation.

13. The method of claim 10 , wherein the first verification module is configured to probe a predetermined signal in response to at least the control information received from the interface.

14. The method of claim 13 , wherein the probing is performed synchronously or asynchronously.

15. The method of claim 10 , wherein the interface is further configured to send commands for reconfiguring a first configured FPGA image of the plurality of configured FPGA images.

16. The method of claim 15 , wherein the reconfiguring of the first configured FPGA image comprises: receiving a modified image of the first configured FPGA image; and reconfiguring data-dependent circuitry of the modified first configured FPGA image associated with the first verification module.

17. The method of claim 10 , wherein the processing comprises decoding the received probed signal values.