Close-Coupling Shared Storage Architecture of Double-Wing Expandable Multiprocessor

1. A close-coupling shared storage architecture of double-wing expandable processors, comprising: at least J processor modules comprised in a close-coupling shared storage architecture of at least P processors; wherein each processor module is formed by coupling and cross-jointing at least I processors, and each processor is directly connected with a node controller through only one link; wherein each processor module comprises two pairing node controllers, and each node controller is connected with one or more of the processors through at least M links and is connected with one or more cross switch route chips of an interconnect network through at least N links; and wherein the interconnect network comprises two groups on two wings of the architecture, and each group is connected with at least K cross switch route chips, each of which has at least Q ports; wherein the number of the at least P processors is P=I×J; wherein to achieve a non-blocking of communications among the at least I processors I=2×M; wherein to achieve a non-blocking of network transmissions N×J=Q×K; wherein a bandwidth of a single link for a processor is at least A, and a bandwidth of a single link for the interconnect network is at least B, where A>B; wherein to keep the relative balance between processor bandwidth and network bandwidth M<N; and wherein the close-coupling shared storage architecture of the processors is constructed on the premise of maintaining high extensibility of system scales, the relative balance between the processor bandwidth and the network bandwidth is achieved, and relatively low average delay of the interconnection network is maintained simultaneously.

2. A close-coupling shared storage architecture of double-wing expandable processors, comprising: an interconnect network comprising two groups, wherein each group is connected with at least K cross-switch route chips and each cross-switch route chip includes at least Q ports; at least P processors; and at least J processor modules, wherein each of the at least J processor modules comprises: at least I coupled and cross-jointed processors, wherein each of the at least I coupled and cross-jointed processors is directly connected with a node controller through only one link, and two pairing node controllers, wherein each node controller is connected with one or more of the at least I coupled and cross-jointed processors through at least M first links and is connected with one or more cross-switch route chips of a group of the interconnect network through at least N second links; wherein the number of the at least P processors is P=I×J; wherein to achieve a non-blocking of communications among the at least I coupled and cross-jointed processors I=2×M; wherein to achieve a non-blocking of network transmissions N×J=Q×K; wherein a bandwidth of a single first link is at least A, and a bandwidth of a single second link is at least B, where A>B; and wherein to keep the relative balance between processor bandwidth and network bandwidth M<N.

3. The close-coupling shared storage architecture of claim 1 , wherein each of A, B, I, J, K, M, N, P, and Q is a positive integer.

4. The close-coupling shared storage architecture of claim 2 , wherein each of A, B, I, J, K, M, N, P, and Q is a positive integer.