8315348

Clock Extraction Circuit for Use in a Linearly Expandable Broadcast Router

PublishedNovember 20, 2012
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
8 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method for extracting selected time information from a stream of serialized Audio Engineering Society (AES) digital audio data, comprising: detecting, by a broadcast router, a first transition indicative of a first preamble of said stream of serialized AES digital audio data; detecting, by the broadcast router, a second transition indicative of a subsequent preamble of said serialized AES digital audio data, wherein said second transition is detected by counting transitions after the first transition where said first transition and said second transition are separated by thirty-one intervening transitions, wherein said thirty-one intervening transitions are not indicative of said subsequent preamble of said serialized AES digital audio data; determining a clock pulse count separating said first preamble and said subsequent preamble; and transferring the determined clock pulse count to a decoding logic circuit for decoding said stream of serialized AES digital audio data by utilizing the determined clock pulse count.

2

2. The method of claim 1 , wherein said determined clock pulse count is suitable for use in encoding said stream of serialized AES digital audio data.

3

3. The method of claim 2 , and further comprising transferring said determined clock pulse count to an encoding logic circuit for use in encoding said stream of serialized AES digital audio data.

4

4. The method of claim 3 , wherein said clock pulse count is a count of clock pulses of a fast clock.

5

5. The method of claim 3 , wherein said first transition and said second transition are separated by thirty-one intervening transitions, wherein said thirty-one intervening transitions are not indicative of said subsequent preamble of said serialized AES digital audio data, and wherein at the thirty-second intervening transition the fast clock pulse count is determined.

6

6. A broadcast router comprising: a decoder circuit coupled to receive a stream of serialized Audio Engineering Society (AES) digital audio data, said decoder circuit extracting time information from said stream of serialized AES digital audio data during the decoding thereof wherein said time information comprises a clock pulse count separating a first transition indicative of a first preamble of said stream of serialized AES digital audio data, and a second transition indicative of a second preamble of said stream of serialized AES digital audio data, wherein said second transition is detected by counting transitions after the first transition where said first transition and said second transition are separated by thirty-one intervening transitions, wherein said thirty-one intervening transitions are not indicative of said subsequent preamble of said serialized AES digital audio data and utilizing said extracted time information to decode said received stream of serialized AES digital audio data; and a target component coupled to said decoder circuit, said target component receiving said extracted time information from said stream of serialized AES digital audio data; wherein said target component utilizes said extracted time information while executing at least one function thereof.

7

7. A method for extracting selected time information from a stream of serialized Audio Engineering Society (AES) digital audio data, comprising: detecting, by a broadcast router, a first transition of the stream of serialized AES digital audio data; counting, by a broadcast router, a number of transitions of the serialized AES digital audio data from the first transition until the number of transition reaches a count of 33; counting a number of clock pulses of a clock from the detecting of the first transition of the serialized AES digital audio data until the number of transitions reaches the count of 33, the clock having a higher frequency than a frequency of the transitions of the serialized AES digital audio data; and outputting the clock count to a decoding logic circuit.

8

8. The method of claim 7 , wherein the clock is a fast clock.

Patent Metadata

Filing Date

Unknown

Publication Date

November 20, 2012

Inventors

Carl L. Christensen
Lynn Howard Arbuckle

Want to explore more patents?

Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.

Citation & reuse

Analysis on this page is generated by Patentable — an AI-powered patent intelligence platform. AI-generated summaries, explanations, and analysis may be reused with attribution and a visible link back to the canonical URL below. Patent abstracts and claims are USPTO public domain.

Cite as: Patentable. “CLOCK EXTRACTION CIRCUIT FOR USE IN A LINEARLY EXPANDABLE BROADCAST ROUTER” (8315348). https://patentable.app/patents/8315348

© 2026 Patentable. All rights reserved.

Patentable is a research and drafting-assistant tool, not a law firm, and does not provide legal advice. Documents we generate are drafts for review by a licensed patent attorney.