Efficient In-Band Reliability with Separate Cyclic Redundancy Code Frames

1. A method comprising: generating an error bit checksum to cover transmission errors for a plurality of data bits over a plurality of User Interval (UI) in length; framing the plurality of data bits in a write data frame, wherein the write data frame is a first multiple of the UI in length; transferring the write data frame to a dynamic random access memory (DRAM) device via one or more lanes of a data interconnect; framing the error bit checksum in a write error bit frame, wherein the write error bit frame is a second multiple of the UI in length; and transferring the write error bit frame to the DRAM device via the one or more lanes of the data interconnect, wherein only a subset of the plurality of UI in length are used to transfer the write error bit frame to the DRAM device in which some of the UI contain the write error bit frame and in which at least some of the UI do not contain the write error bit frame.

2. The method of claim 1 , further comprising: receiving an indication that a transmission error associated with the data frame was detected based, at least in part, on the error bit checksum; and resending the data frame to the DRAM device.

3. The method of claim 1 , further comprising: issuing a first write command indicating that the write data frame is to be written to the DRAM device; and issuing a second write command indicating that the error bit frame is to be written to the DRAM device.

4. The method of claim 1 , further comprising: issuing a single write command indicating that the write data frame and the error bit frame are to be written to the DRAM device.

5. The method of claim 1 , further comprising: receiving a read data frame from the DRAM device, the read data frame including a plurality of read data bits; and receiving a read error bit frame from the DRAM device, wherein the read error bit frame includes a checksum covering at least some of the plurality of read data bits.

6. The method of claim 5 , further comprising: issuing a first read command indicating that the read data frame is to be read from the DRAM device; and issuing a second read command indicating that the read error bit frame is to be read from the DRAM device.

7. The method of claim 5 , further comprising: issuing a single read command indicating that the read data frame and the read error bit frame are to be read from the DRAM device.

8. A dynamic random access memory (DRAM) device comprising: receiving logic to receive a write data frame over a plurality of User Interval (UI) in length, wherein the write data frame is a first multiple of the UI in length, and a write error bit frame, wherein the write error bit frame is a second multiple of the UI in length, from a host, wherein the write error bit frame includes a checksum to cover one or more data bits of the write data frame, and wherein only a subset of the plurality of UI in length are used to transfer the write error bit frame to the DRAM device from the host, in which some of the UI contain the write error bit frame and in which at least some of the UI do not contain the write error bit frame; write error bit generation logic to receive as an input the one or more data bits of the data frame and to provide as an output a locally generated checksum; and comparison logic to compare the checksum with the locally generated checksum.

9. The device of claim 8 , further comprising: a memory array to provide one or more read data bits; read error bit generation logic to generate a read checksum; a transmit framing unit to generate a read data frame based on the read data bits and to generate a read error bit frame based on the read checksum.

10. The device of claim 9 , wherein the write error bit generation logic and the read error bit generation logic are the same.

11. The device of claim 9 , wherein the read data frame is M user intervals (UI) long.

12. The device of claim 11 , wherein M is eight.

13. The device of claim 11 , wherein the read error bit frame is N UI long.

14. The device of claim 13 , wherein N is a multiple of four.

15. An integrated circuit comprising: error bit generation logic having as an input a plurality of write data bits to be transferred to a dynamic random access memory (DRAM) device over a plurality of User Interval (UI) in length and having as an output a write checksum to cover the plurality of write data bits; and a framing unit to frame a write data frame, wherein the write data frame is a first multiple of the UI in length, based on the write data bits and a write error bit frame, wherein the write error bit frame is a second multiple of the UI in length, based on the write checksum, wherein only a subset of the plurality of UI in length are to be used to transfer the write error bit frame to the DRAM device in which some of the UI contain the write error bit frame and in which at least some of the UI do not contain the write error bit frame.

16. The integrated circuit of claim 15 , further comprising: command logic to issue write commands to the DRAM device, wherein the command logic is capable of issuing a write data command to indicate that a data frame is being written to memory and a write error bits command to indicate that a write error bit frame is being written to the DRAM device.

17. The integrated circuit of claim 16 , wherein the command logic is capable of issuing a single write command to indicate that both a data frame and an error bit frame are being written to the DRAM device.

18. The integrated circuit of claim 15 , further comprising: a receive framing unit to receive a read data frame and a read error bit frame from the DRAM device, wherein the read data frame includes a plurality of read data bits and the read error bit frame includes a checksum covering at least a portion of the plurality of read data bits; logic to generate a local checksum based, at least in part, on the plurality of read data bits; and comparison logic to compare the local checksum with the local checksum.

19. The integrated circuit of claim 18 , further comprising: command logic to issue read commands to the DRAM device, wherein the command logic is capable of issuing a read data command to indicate that the read data frame is being read from memory and a read error bits command to indicate that the read error bit frame is being read from the DRAM device.

20. The integrated circuit of claim 19 , wherein the command logic is capable of issuing a single read command to indicate that both the read data frame and the read error bit frame are being read from the DRAM device.

21. The integrated circuit of claim 15 , further comprising: logic to selectively enable error protection to cover the plurality of write data bits.

22. The integrated circuit of claim 15 , wherein the plurality of write data bits are arranged in a serpentine pattern across two or more columns of the write data frame.

23. A system comprising: a host including, error bit generation logic having as an input a plurality of write data bits to be transferred to a dynamic random access memory (DRAM) device over a plurality of User Interval (UI) in length and having as an output a write checksum to cover the plurality of write data bits, and a framing unit to frame a write data frame, wherein the write data frame is a first multiple of the UI in length, based on the write data bits and a write error bit frame, wherein the write error bit frame is a second multiple of the UI in length, based on the write checksum; and a dynamic random access memory (DRAM) device coupled to the host via a memory interconnect to receive transfer of the write error bit frame from the host, wherein only a subset of the plurality of UI in length are used to transfer the write error bit frame to the DRAM device in which some of the UI contain the write error bit frame and in which at least some of the UI do not contain the write error bit frame.

24. The system of claim 23 , wherein the host further includes command logic to issue write commands to the DRAM device, wherein the command logic is capable of issuing a write data command to indicate that a data frame is being written to memory and a write error bits command to indicate that a write error bit frame is being written to the DRAM device.

25. The system of claim 24 , wherein the command logic is capable of issuing a single write command to indicate that both a data frame and an error bit frame are being written to the DRAM device.

26. The system of claim 23 , wherein the host further includes a receive framing unit to receive a read data frame and a read error bit frame from the DRAM device, wherein the read data frame includes a plurality of read data bits and the read error bit frame includes a checksum covering at least a portion of the plurality of read data bits; logic to generate a local checksum based, at least in part, on the plurality of read data bits; and comparison logic to compare the local checksum with the checksum.

27. The system of claim 26 , wherein the host further includes command logic to issue read commands to the DRAM device, wherein the command logic is capable of issuing a read data command to indicate that the read data frame is being read from memory and a read error bits command to indicate that the read error bit frame is being read from the DRAM device.

28. The system of claim 27 , wherein the command logic is capable of issuing a single read command to indicate that both the read data frame and the read error bit frame are being read from the DRAM device.

29. The system of claim 23 , wherein the DRAM device comprises: receiving logic to receive the write data frame and the write error bit frame from the host; write error bit generation logic to receive as an input the one or more data bits of the write data frame and to provide as an output a locally generated checksum; and comparison logic to compare the checksum with the locally generated checksum.

30. The system of claim 29 , wherein the DRAM device further comprises: a memory array to provide one or more read data bits; read error bit generation logic to generate a read checksum; a transmit framing unit to generate a read data frame based on the read data bits and to generate a read error bit frame based on the read checksum.

31. The system of claim 30 , wherein the write error bit generation logic and the read error bit generation logic are the same.

32. The system of claim 23 , wherein the host is integrated onto the same die as one or more processors.