Method and System for Routing Data in a Parallel Turbo Decoder

1. A method for routing data in a parallel Turbo decoder, wherein the parallel Turbo decoder comprises a plurality of processors and a plurality of memory banks, said method comprising: associating a memory bank with a processor; addressing a data item; and routing the addressed data item between the associated memory bank and the processor, wherein the processor is associated with the memory bank that is indexed according to a function of a position of the data item, wherein a memory bank index is the position of the data item divided by a length of an interleaver sub-block, wherein any remainder of the division is disregarded, wherein the data item is addressed according to a function of the position of the data item, wherein a data item address is the remainder of the division of the position of the data item by the length of the interleaver sub-block.

2. The method of claim 1 , wherein the processor determines an index of the associated memory bank.

3. The method of claim 1 , wherein an address generation module addresses the data item within the associated memory bank.

4. The method of claim 1 , wherein a data routing network routes the addressed data item between the associated memory bank and the processor.

5. The method of claim 4 , wherein the data routing network coordinates the association of the data item with the processor.

6. A method for routing data in a parallel Turbo decoder, wherein the parallel Turbo decoder comprises a plurality of processors and a plurality of memory banks, said method comprising: associating a memory bank with a processor; addressing a data item; and routing the addressed data item between the associated memory bank and the processor, wherein the processor is associated with the memory bank that is indexed according to a function of a data item position, wherein a memory bank index is a remainder of a division of the data item position by a number of processors in the plurality of processors, wherein the data item is addressed according to a function of the position of the data item, wherein a data item address is the remainder of the division of the position of the data item by the length of the interleaver sub-block.

7. A system for routing data in a parallel Turbo decoder, said system comprising: a plurality of processors; a plurality of memory banks, wherein, at a point in a decoding process, a memory bank in the plurality of memory banks is associated with a processor in the plurality of processors; a plurality of address generation modules, wherein an address generation module addresses a data item; and a data routing network for routing the addressed data item from the associated memory bank to the processor, wherein the processor is associated with the memory bank that is indexed according to a function of a position of the data item, wherein a memory bank index is the position of the data item divided by a length of an interleaver sub-block, wherein any remainder of the division is disregarded, wherein the data item is addressed according to a function of the position of the data item, wherein a data item address is the remainder of the division of the position of the data item by the length of the interleaver sub-block.

8. The system of claim 7 , wherein the processor determines the index of the associated memory bank.

9. The system of claim 7 , wherein each address generation module in the plurality of address generation modules is connected to one of the memory banks in the plurality of memory banks.

10. The system of claim 7 , wherein the data routing network routes the addressed data item to the associated memory bank from the processor.

11. The system of claim 10 , wherein the data routing network coordinates the association of the data item with the processor.

12. A system for routing data in a parallel Turbo decoder, said system comprising: a plurality of processors; a plurality of memory banks, wherein, at a point in a decoding process, a memory bank in the plurality of memory banks is associated with a processor in the plurality of processors; a plurality of address generation modules, wherein an address generation module addresses a data item; and a data routing network for routing the addressed data item from the associated memory bank to the processor, wherein the processor is associated with the memory bank that is indexed according to a function of a position of the data item, wherein a memory bank index is a remainder of a division of the data item a number of processors in the plurality of processors, wherein the data item is addressed according to a function of the position of the data item, wherein a data item address is the remainder of the division of the position of the data item by the length of the interleaver sub-block.