Method for Identifying a Flash Memory Device and Related Hosting Device

1. A method for identifying a flash memory device coupled to a host device, the flash memory device having a page size from a plurality of possible page sizes, bootstrap code stored on a first sector thereof, and a data bus for accessing data stored thereon and with a data bus size from a plurality of possible data bus sizes, the method comprising: reading the bootstrap code stored in a first page of the first sector as if the flash memory device had an assumed page size and an assumed data bus size; and verifying whether two nonconsecutive bytes of the bootstrap code are correct, and if not, generating a signal indicating that the flash memory device does not have the assumed page size and the assumed data bus size, otherwise executing at least reading content from memory locations where error correction code (ECC) bytes of the first page are stored if the flash memory device has the assumed page size and checking whether the ECC bytes include more than a number of errors associated with the assumed page size, and if the ECC bytes do not include more than the number of errors, generating a signal that the flash memory device has the assumed page size and the assumed data bus size.

2. The method according to claim 1 wherein the flash memory device comprises a NAND flash memory device.

3. The method according to claim 1 wherein the page size and the data bus size are identified without reading identification code from the flash memory device.

4. The method according to claim 1 wherein the number of errors is one.

5. The method according to claim 1 wherein the number of errors is eight.

6. The method according to claim 1 wherein the reading of the bootstrap code stored in the first page of the first sector is based upon a number of bytes of data of the first page corresponding to a page of data of a Small Page memory device.

7. The method according to claim 1 wherein the page size is based upon a Large Page size and the data bus size is 8 bits; and further comprising: if a logic high output signal is generated, generating signals for identifying the flash memory device as having the page size and the data bus size, otherwise if not all combinations of the possible page sizes and the possible data bus sizes have been tried, executing for a different combination of possible page size and possible data bus size and repeating the generating of the signals for identifying the memory if the logic high output signal is generated, otherwise generating signals for indicating that the flash memory device has not been identified.

8. The method according to claim 1 wherein the plurality of possible page sizes includes a Large Page size, a Very Large Page size, and a Small Page size; and wherein the plurality of possible data bus sizes includes 8-bit and 16-bit.

9. The method according to claim 1 wherein the two nonconsecutive bytes are the first and the third bytes.

10. A method for operating a microprocessor host system to generate a flag signal upon recognizing a NAND flash memory device with a bootstrap code in a first sector thereof, the NAND flash memory device being connected to the microprocessor host system and having a page size belonging to a group of possible page sizes and a data bus for accessing content stored in the NAND flash memory device and having a data bus size belonging to a group of possible data bus sizes without reading identification code from the NAND flash memory device, the method comprising: reading data written in a first page of the first sector as if the NAND flash memory device had an assumed page size and an assumed data bus size; and verifying whether two nonconsecutive bytes of the bootstrap code are correct, and if not, generating a signal indicating that the NAND flash memory device does not have the assumed page size and the assumed data bus size, otherwise executing at least reading content of memory locations where error correction code (ECC) bytes of the first page are stored if the NAND flash memory device has the assumed page size and checking whether the ECC bytes include more than a pre-established number of errors, and if the ECC bytes do not include more than the pre-established number of errors, generating the flag signal that the NAND flash memory device has the assumed page size and the assumed data bus size.

11. The method according to claim 10 wherein the pre-established number of errors is one.

12. The method according to claim 10 wherein the pre-established number of errors is eight.

13. The method according to claim 10 wherein the reading of the data written in the first page of the first sector is carried out on a number of bytes of data of the first page corresponding to a page of data of a Small Page memory device.

14. The method according to claim 10 wherein the page size is based upon a Large Page size and the data bus size is 8 bits; and further comprising: if a logic high output signal is generated, generating identification signals for identifying the NAND flash memory device as having the page size and the data bus size, otherwise if not all combinations of the possible page sizes and the possible data bus sizes have been tried, executing for a different combination of possible page size and possible data bus size and repeating the generating of the identification signals for identifying the memory if the logic high output signal is generated, otherwise generating identification signals for indicating that the NAND flash memory device has not been identified.

15. The method according to claim 10 wherein the group of possible page sizes includes a Large Page size, a Very Large Page size, and a Small Page size; and wherein the group of possible data bus sizes includes 8-bit and 16-bit.

16. The method according to claim 10 wherein the two nonconsecutive bytes are the first and the third bytes.

17. The method according to claim 10 wherein the page size is based upon a Large Page; wherein the data bus size is 8 bits; and further comprising: if a logic high output signal is generated, generating identification signals for identifying the NAND flash memory device as having the assumed page size and the assumed data bus size, otherwise if not all combinations of possible page sizes and possible data bus sizes have been tried, executing for a different combination of possible page sizes and possible data bus sizes and repeating the generating of the identification signals for identifying the memory if the logic high output signal is generated, otherwise generating identification signals for indicating that the NAND flash memory device has not been identified.

18. A host device to be coupled to a flash memory device, the flash memory device having a page size from a plurality of possible page sizes, bootstrap code stored on a first sector thereof, and a data bus for accessing data stored thereon and with a data bus size from a plurality of possible data bus sizes, the host device comprising: a memory; a processor cooperating with said memory and configured to read the bootstrap code stored in a first page of the first sector as if the flash memory device had an assumed page size and an assumed data bus size, and verify whether two nonconsecutive bytes of the bootstrap code are correct, and if not, generating a signal indicating that the flash memory device does not have the assumed page size and the assumed data bus size, otherwise executing at least read content from memory locations where error correction code (ECC) bytes of the first page are stored if the flash memory device has the assumed page size and checking whether the ECC bytes include more than a number of errors associated with the assumed page size, and if the ECC bytes do not include more than the number of errors, generate a signal that the flash memory device has the assumed page size and the assumed data bus size.

19. The host device according to claim 18 wherein the flash memory device comprises a NAND flash memory device.

20. The host device according to claim 18 wherein the page size and the data bus size are identified without reading identification code from the flash memory device.

21. The host device according to claim 18 wherein the number of errors is one.

22. The host device according to claim 18 wherein the number of errors is eight.