Apparatus and Method for Driving Display Panel Including Control of Charge Pump

1. A display panel drive apparatus comprising: a drive circuit outputting drive voltages to a display panel in response to a timing control signal used for timing control of image display on said display panel; and a booster circuit feeding a boosted power supply voltage to said drive circuit, said booster circuit including: a charge pump circuit generating said boosted power supply voltage by boosting an input power supply voltage in response to a boosting clock; a comparator receiving the generated boosted power supply voltage and comparing with a reference voltage to output a comparison result; and a pulse skip circuit monitoring a voltage level of said boosted power supply voltage and controlling a boosting operation of said charge pump circuit in response to said voltage level of said boosted power supply voltage, wherein said pulse skip circuit is configured to selectively allow said charge pump circuit to initiate said boosting operation in synchronization with said timing control signal including a first timing control signal for setting an impedance state of the drive circuit, wherein the pulse skip circuit comprises: a flip-flop receiving the comparison result from the comparator at a clock input and the input power supply voltage to selectively allow said charge pump circuit to initiate said boosting operation in synchronization with said timing control signal; a NOT circuit receiving the comparison result from the comparator; and an OR circuit outputting, an OR logical operation of an output of the NOT circuit and the timing control signal, to a reset input of the flip-flop.

2. The display panel drive apparatus according to claim 1 , wherein said charge pump circuit boosts said input power supply voltage when said boosting clock is supplied to said charge pump circuit, and stops boosting said input power supply voltage when said boosting clock stops being supplied to said charge pump circuit, and wherein said pulse skip circuit controls supply of said boosting clock to said charge pump circuit.

3. The display panel drive apparatus according to claim 1 , wherein said pulse skip circuit includes a skip signal control circuit configured to allow supplying said boosting clock to said charge pump circuit in response to said timing control signal, when said boosted power supply voltage is less than a predetermined output reference voltage.

4. The display panel drive apparatus according to claim 3 , wherein said skip signal control circuit is configured to prohibit supplying said boosting clock to said charge pump circuit when said boosted power supply voltage exceeds said predetermined output reference voltage.

5. The display panel drive apparatus according to claim 1 , further comprising: a power supply voltage monitoring circuit monitoring said input power supply voltage, wherein said pulse skip circuit includes a skip signal control circuit configured to allow supplying said boosting clock to said charge pump circuit in response to said timing control signals when said power supply voltage monitoring circuit detects that said input power supply voltage exceeds a predetermined input reference voltage.

6. The display panel drive apparatus according to claim 5 , wherein said skip signal control circuit is configured to prohibit supplying said boosting clock to said charge pump circuit when said boosted power supply voltage exceeds said predetermined output reference voltage.

7. The display panel drive apparatus according to claim 5 , wherein, in a case that said input power supply voltage is less than said predetermined input reference voltage, said skip signal control circuit allows supplying said boosting clock to said charge pump circuit when said boosted power supply voltage is less than said predetermined output reference voltage and prohibits supplying said boosting clock when said boosted power supply voltage exceeds said predetermined output reference voltage.

8. The display panel drive apparatus according to claim 1 , wherein said timing control signal includes a Hi-Z (high-impedance) signal in response to which outputs of said drive circuit are set to high-impedance, and wherein said pulse skip circuit supplies said boosting clock to said charge pump circuit when said outputs of said drive circuit are set to high-impedance.

9. The display panel drive apparatus according to claim 8 , wherein a cycle of said boosting clock is twice as long as said timing control signal, and a rising edge or falling edge of said boosting clock is positioned in a period during which said outputs of said drive circuit are set to high-impedance.

10. The display panel drive apparatus according to claim 1 , wherein said timing control signal includes a Hi-Z (high-impedance) signal in response to which outputs of said drive circuit are set to high-impedance, and wherein said pulse skip circuit supplies said boosting clock to said charge pump circuit when said boosted power supply voltage is less than a predetermined output reference voltage and said outputs of said drive circuit are set to high-impedance.

11. The display panel drive apparatus according to claim 10 , further comprising: a power supply voltage monitoring circuit monitoring said input power supply voltage, wherein, when said power supply voltage monitoring circuit detects that said input power supply voltage exceeds a predetermined input reference voltage, said pulse skip circuit supplies said boosting clock to said charge pump circuit in a period during which said boosted power supply voltage is less than said predetermined output reference voltage and said outputs of said drive circuit are set to high-impedance.

12. The display panel drive apparatus according to claim 11 , wherein, in a case that said input power supply voltage is less than said predetermined input reference voltage, said pulse skip circuit supplies said boosting clock to said charge pump circuit when said boosted power supply voltage is less than said predetermined output reference voltage, stops supplying said boosting clock when said boosted power supply voltage exceeds said predetermined output reference voltage.

13. The display panel drive apparatus according to claim 1 , wherein said booster circuit comprises another charge pump circuit that operates on another boosting clock having a phase opposite to said boosting clock.

14. The display panel drive apparatus according to claim 1 , wherein the charge pump circuit starts the boosting operation in response to an activation of the first timing control signal to selectively operate during periods of time including high-impedance periods of the drive circuit.

15. The display panel drive apparatus according to claim 1 , wherein the timing control signal comprises the first timing control signal and a clock signal from a control circuit to selectively allow the boosting operation to begin in synchronization with the timing control signal and restrict operation during time periods according to a high-impedance state of the drive circuit.

16. The display panel drive apparatus according to claim 1 , wherein the pulse skip circuit further comprises a plurality of logic gates connected to the flip-flop, wherein the flip-flop with the plurality of logic gates selectively allows said charge pump circuit to initiate said boosting operation in synchronization with said timing control signal.

17. The display panel drive apparatus according to claim 1 , wherein the flip-flop and a plurality of logic gates selectively enables or disables the boosting operations during periods of time according to the impedance state of the drive circuit.

18. The display panel drive apparatus according to claim 1 , wherein the boosting clock is generated such that one of a rising edge and a falling edge is located in a high-impedance period.

19. The display panel drive apparatus according to claim 1 , wherein the boosting clock is generated such that one of a rising edge or a falling edge of the boosting clock equally divides each of high-impedance periods into at least two periods of a same duration, the high-impedance periods being when the input power supply voltage is high enough to cause a horizontally-striped noise.

20. The display panel drive apparatus according to claim 1 , wherein the timing control signal is synchronized with the first timing control signal for setting the impedance state of outputs of the drive circuit, and wherein the drive voltages are outputted from the outputs of the drive circuit to the display panel.

21. A display device comprising: a display panel; and a display panel driver apparatus, wherein said display panel driver includes: a drive circuit outputting drive voltages to said display panel in response to a timing control signal used for timing control of image display on said display panel; and a booster circuit feeding a boosted power supply voltage to said drive circuit, said booster circuit comprising: a charge pump circuit generating said boosted power supply voltage by boosting an input power supply voltage in response to a boosting clock to generate; a comparator receiving the generated boosted power supply voltage and comparing with a reference voltage to output a comparison result; and a pulse skip circuit monitoring a voltage level of said boosted power supply voltage and controlling an a boosting operation of said charge pump circuit in response to said voltage level of said boosted power supply voltage, wherein said pulse skip circuit is configured to selectively allow said charge pump circuit to initiate said boosting operation in synchronization with said timing control signal including a signal setting an impedance state of the drive circuit wherein the pulse skip circuit comprises: a flip-flop receiving the comparison result from the comparator at a clock input and the input power supply voltage to selectively allow said charge pump circuit to initiate said boosting operation in synchronization with said timing control signal; a NOT circuit receiving the comparison result from the comparator; and an OR circuit outputting, an OR logical operation of an output of the NOT circuit and the timing control signal, to a reset input of the flip-flop.

22. The display device according to claim 21 , wherein the timing control signal is synchronized with the signal for setting the impedance state of outputs of the drive circuit, and wherein the drive voltages are outputted from the outputs of the drive circuit to the display panel.

23. A method of driving a display panel comprising: generating a boosted power supply voltage by a charge pump circuit through boosting an input power supply voltage in response to a boosting clock; monitoring said boosted power supply voltage by a pulse skip circuit; controlling said boosting in response to said boosted power supply voltage that is monitored; and outputting drive voltages to a display panel in response to a timing control signal used for timing control of image display on said display panel, wherein said controlling said boosting includes selectively allowing said boosting of said input power supply voltage in response to said timing control signal including instructions of an impedance state of a drive circuit for the outputting of drive voltages to the display panel, wherein the monitoring by the pulse skip circuit comprises: receiving, by a flip-flop, said boosted power supply voltage that is monitored at a clock input and the input power supply voltage to selectively allow said charge pump circuit to initiate said boosting operation in synchronization with the timing control signal; receiving, by a NOT circuit, the comparison result from the comparator; and outputting, by an OR circuit, an OR logical operation of an output of the NOT circuit and the timing control signal, to a reset input of the flip-flop.

24. The method according to claim 23 , wherein said controlling said boosting includes allowing a supplying of said boosting clock to said charge pump circuit in response to said timing control signal when said boosted power supply voltage is less than a predetermined output reference voltage.

25. The method according to claim 23 , further comprising: monitoring said input power supply voltage; and allowing a supplying of said boosting clock to said charge pump circuit in response to said timing control signal when said input power supply voltage exceeds a predetermined input reference voltage.

26. The method according to claim 25 , wherein, for a case that said input power supply voltage is less than said predetermined input reference voltage, supply of said boosting clock to said charge pump circuit is allowed when said output voltage is less than said predetermined output reference voltage, and is prohibited when said output voltage exceeds said predetermined output reference voltage.

27. The method according to claim 23 , wherein said timing control signal includes a Hi-Z (high-impedance) signal instructing a drive circuit to set outputs thereof to high-impedance, said drive voltage being outputted through said outputs of said drive circuit, and wherein said boosting clock is supplied to said charge pump circuit in a period during which said boosted power supply voltage is less than a predetermined output reference voltage and said outputs of said drive circuit are set to high-impedance.

28. The display panel drive apparatus according to claim 27 , further comprising: monitoring said input power supply voltage; and supplying said boosting clock to said charge pump circuit in a period during which said boosted power supply voltage is less than a predetermined output reference voltage and said outputs of said drive circuit are set to high-impedance, when said input power supply voltage exceeds a predetermined input reference voltage.

29. The method according to claim 23 , wherein the timing control signal is synchronized with the instructions for setting the impedance state of outputs of the drive circuit, and wherein the drive voltages are outputted from the outputs of the drive circuit to the display panel.