Reduced Memory Usage for Digital Signal Processing System and Method

1. A method of reducing memory usage for storage of intermediate data results during digital signal processing, comprising: performing a digital signal processing operation to produce a plurality of intermediate data results, each of the plurality of intermediate data results having a most significant portion and a least significant portion; storing the least significant portions of the plurality of intermediate data results in a first memory array having a first length; selecting a subset of the plurality of intermediate data results that meet a predefined criteria, wherein the selected subset comprises less than all of the plurality of intermediate data results; storing the most significant portions of only the selected subset of the plurality of intermediate data results in a second memory array having a second length smaller than the first length, wherein the most significant portions of the intermediate data results not in the selected subset are not stored in the second memory; and maintaining linkage data for each individual one of the most significant portions stored in the second memory array at the step of storing the most significant portions, wherein the linkage data links each one of the individual most significant portions stored in the second memory array at the step of storing the most significant portions to the corresponding least significant portion stored in the first memory array at the step of storing the least significant portions.

2. The method of claim 1 , wherein the predefined criteria is that the least significant portion has overflowed into the most significant portion.

3. The method of claim 1 , wherein the predefined criteria is that the most significant portion contains information necessary to the signal processing operation.

4. The method of claim 1 , wherein performing a digital signal processing operation comprises estimating a correlation.

5. The method of claim 4 , wherein the correlation is estimated for at least 5,000 different time positions.

6. The method of claim 1 , wherein maintaining linkage data comprises: augmenting the least significant portions of the intermediate data results with a linkage bit; and setting the linkage bits for the subset of the plurality of intermediate data results.

7. The method of claim 1 , wherein maintaining linkage data comprises storing memory addresses into the second memory array along with the most significant portions, wherein the memory addresses correspond to locations within the first memory array of the corresponding least significant portions.

8. The method of claim 1 further comprising: fetching least significant portions of the plurality of intermediate data results from the first memory; fetching corresponding most significant portions of the subset of the plurality of intermediate data results from the second memory when a most significant portion has been stored in the second memory; and extending a sign of the least significant portion of the plurality of intermediate data results when a corresponding most significant portion has not been stored in the second memory.

9. The method of claim 1 further comprising selecting the second length based on characteristics of the signal processing operation.

10. A device for reducing memory usage in a digital signal processing system comprising: a digital signal processor configured to operate on a plurality of intermediate data results; means for storing least significant portions of the plurality of intermediate data results; means for selecting a subset of the plurality of intermediate data results that meet a predefined criteria, wherein the selected subset comprises less than all of the plurality of intermediate data results; means for storing most significant portions of only the selected subset of the plurality of intermediate data results, wherein the most significant portions of the intermediate data results not in the selected subset are not stored in the second memory; and means for reconstructing most significant portions of the subset of the plurality of intermediate data results upon retrieval of the corresponding least significant portions, wherein the means for reconstructing utilizes stored linkage data that links individual ones of the most significant portions stored by the means for storing most significant portions to its corresponding least significant portion stored by the means for storing least significant portions.

11. The device of claim 10 wherein the means for storing most significant portions of the subset of the plurality of intermediate data results comprises means for detecting an overflow in the least significant portions.

12. The device of claim 10 wherein the means for reconstructing most significant portions of the subset of the plurality of intermediate data results comprises means for extending a sign of the least significant portions.

13. The device of claim 10 wherein the digital signal processor is a correlator having at least 5000 taps.

14. A device for reducing memory usage in a signal processing system, the device comprising: a signal processor having a memory interface for storage and retrieval of a plurality of intermediate data results, each of the intermediate data results being separable into a most significant portion and a least significant portion; a first memory coupled to the memory interface to store the least significant portions of the plurality of intermediate data results, the first memory having a first width and a first length; a second memory coupled to the memory interface to store the most significant portions of only a selected subset of the plurality of intermediate data results, the second memory having a second width and a second length, the second length being less than the first length, wherein the selected subset comprises less than all of the plurality of intermediate data results; and a tracker coupled to the first memory and the second memory to maintain linkage data for each of the individual most significant portions of the intermediate data results stored in the second memory, wherein the linkage data links each individual one the most significant portions stored in the second memory to its corresponding least significant portion stored in the first memory.

15. The device of claim 14 , wherein the signal processor is a correlator.

16. The device of claim 15 , wherein the first length is at least 5000, each of 5000 memory locations within the first memory corresponding to a different time hypothesis for the correlator.

17. The device of claim 14 , wherein the first memory and the second memory are memory devices chosen from the group consisting of random access memory, shift register memory, register file memory, first in first out memory, dual port memory, logic blocks within a field programmable gate array, and combinations thereof.

18. The device of claim 14 , wherein the tracker comprises: an overflow detector circuit configured to load a most significant portion of an input result into the second memory when an overflow of a least significant portion of the input result detected; and a sign extender circuit coupled to the first memory and configured to sign extend a least significant portion of an output result when no corresponding most significant portion of the output result is available from the second memory.

19. The device of claim 14 , wherein the tracker comprises: a counter coupled to the second memory, the second memory configured to store a stored count value of the counter when a most significant portion is written into the second memory and the second memory configured to output a most significant portion when a count value of the counter is equal to the stored count value.

20. The device of claim 14 , wherein the first width is equal to width of the least significant portions.

21. The device of claim 14 , wherein the second width is equal to width of the most significant portions.

22. The device of claim 14 , wherein the second length is equal to or less than one tenth of the first length.

23. The device of claim 22 , wherein the second length is equal to or less than one hundredth of the first length.