Reducing Runtime Coherency Checking with Global Data Flow Analysis

1. A method, in a data processing system, for reducing runtime coherency checking, the method comprising: responsive to a call being issued during execution of a compiled and optimized code, determining whether the call is for at least one of a DMA get operation to read data from memory into a direct buffer or a DMA put operation to write data from the direct buffer to the memory; responsive to the call being the DMA get operation, determining whether a software cache write operation has been issued to a software controlled cache for the since a last flush operation; and responsive to the software cache write operation being issued to the software controlled cache for the data since the last flush operation, performing a DMA get runtime coherency check between the software controlled cache and the direct buffer.

2. The method of claim 1 , wherein performing the DMA gel runtime coherency check comprises: determining whether the data that is to be retrieved from memory by the DMA get operation already exists in the software controlled cache; responsive to the data existing in the software controlled cache, determining whether any portion of the data that is read into the direct buffer has been modified in the software controlled cache; responsive to a portion of the data that is read into the direct buffer being modified in the software controlled cache, waiting for the DMA get operation for the direct buffer to finish; and copying the data from the software controlled cache into the direct buffer.

3. The method of claim 1 , further comprising: responsive to the software cache write operation failing to be issued to the software controlled cache since the last flush operation, skipping the DMA get runtime coherency check; and, retrieving the data from memory into the direct buffer.

4. The method of claim 1 , further comprising: responsive to the call being the DMA put operation, determining whether the software cache write operation has been issued to the software controlled cache for the data since the last flush operation; responsive to the software cache write operation being issued for the data since the last flush operation, performing a DMA put runtime coherency check between the direct buffer and the software controlled cache; and writing the data from the direct buffer to the memory.

5. The method of claim 4 , wherein performing the DMA put runtime coherency check comprises: determining whether data that is to be written by the DMA put operation already exists in the software controlled cache; and responsive to the data existing in the software controlled cache, copying the data from the direct buffer into the software controlled cache.

6. The method of claim 1 , further comprising: responsive to the call being the DMA put operation, determining whether the software cache write operation has been issued to the software controlled cache for the data since the last flush operation; responsive to the software cache write operation to the software controlled cache for the data failing to be issued since the last flush operation, determining whether a software cache read operation has been issued to the software controlled cache for the data since the last flush operation; responsive to the software cache read operation being issued to the software controlled cache for the data since the last flush operation, determining whether the software cache read operation precedes the DMA put operation from the direct buffer to the memory; and responsive to the software cache read operation preceding the DMA operation from the direct buffer to the memory, performing a DMA put runtime coherency check between the direct buffer and the software controlled cache.

7. The method of claim 6 , further comprising: responsive to the software cache read operation following the DMA put operation from the direct buffer to the memory, skipping the DMA put runtime coherency check.

8. The method of claim 6 , further comprising: responsive to the software cache read operation failing to be issued to the software controlled cache for the data since the last flash operation, skipping the DMA put runtime coherency check.

9. A computer program product comprising a non-transitory computer recordable medium having a computer readable program recorded thereon, wherein the computer readable program, when executed on a computing device, causes the computing device to: responsive to a call being issued during execution of a compiled and optimized code, determine whether the call is for at least one of a DMA get operation to read data from memory into a a direct buffer or a DMA put operation to write data from the direct buffer to the memory; responsive to the call being the DMA get operation, determine whether a software cache write operation has been issued to a software controlled cache for the data since a last flush operation; and responsive to the software cache write operation being issued to the software controlled cache for the data since the last flush operation, perform a DMA get runtime coherency check between the software controlled cache and the direct buffer.

10. The computer program product of claim 9 , wherein the computer readable program to perform the DMA get runtime coherency cheek further includes computer readable program that causes the computing device to: determine whether the data that is to be retrieved front memory by the DMA get operation already exists in the software controlled cache; responsive to the data existing in the software controlled cache, determine whether any portion of the data that is read into the direct buffer has been modified in the software controlled cache; responsive to a portion of the data that is read into the direct buffer being modified in the software controlled cache, wait for the DMA get operation for the direct buffer to finish; and copy the data from the software controlled cache into the direct buffer.

11. The computer program product of claim 9 , wherein the computer readable program further causes the computing device to: responsive to the software cache write operation failing to be issued to the software controlled cache since the last flush operation, skip the DMA get runtime coherency check; and retrieve the data from memory into the direct buffer.

12. The computer program product of claim 9 , wherein the computer readable program further causes the computing device to: responsive to the call being the DMA put operation, determine, whether the software cache write operation has been issued to the so ware controlled cache for the data since the last flush operation; responsive to the software cache write operation being issued to the software controlled cache for the data since the last flush operation, perform a DMA put runtime coherency check between the direct buffer and the software controlled cache; and write the data from the direct buffer to the memory.

13. The computer program product of claim 12 , wherein the computer readable program to perform the DMA put runtime coherency check further includes computer readable program that causes the computing device to; determine whether data that is to be written by the DMA put operation already exists in the software controlled cache, and responsive to the data existing in the software controlled cache, copy the data from the direct buffer into the software controlled cache.

14. The computer program product of claim 9 , wherein the computer readable program further causes the computing device to responsive to the call being the DMA put operation, determine whether the software cache write operation has been issued to the software controlled cache for the data since the last flush operation; responsive to the software cache write operation failing to be issued to the software controlled cache for the data since the last flush operation, determine whether a software cache read operation has been issued to the software controlled cache for the data since the last flush operation; responsive to the software cache read operation being issued to the software controlled cache for the data since the last flush operation, determine whether the software cache read operation precedes the DMA put operation from the direct buffer to the memory; and responsive to the software cache read operation preceding the DMA put operation from the direct buffer to the memory, perform a DMA put runtime coherency check between the direct buffer and the software controlled cache.

15. An apparatus, comprising: a processor; and a memory coupled to the processor, wherein the memory comprises instru which, when executed by the processor, cause the processor to: responsive to a call being issued during execution of a compiled and optimized code, determine whether the call is for at least one of a DMA get operation to read data from memory into a direct buffer or a DMA put operation to write data from the direct buffer to the memory; responsive to the call being the DMA get operation, determine whether a software cache write operation has been issued to a software controlled cache for the data since a last flush operation; and responsive to the software cache write operation being issued to the software controlled cache for the data since the last flush operation, perform a DMA get runtime coherency check between the software controlled cache and the direct buffer.

16. The apparatus of claim 15 , wherein the instructions to perform the DMA get runtime coherency check further cause the processor to: determine whether the data that is to be retrieved from memory by the DMA operation already exists in the software controlled cache; responsive to the data existing in the software controlled cache, determine whether any portion of the data that is read into the direct buffer has been modified in the software controlled cache; responsive to a portion of the data that is read into the direct buffer being modified in the software controlled cache, wait for the DMA get operation for the direct buffer to finish; and copy the data from the software controlled cache into the direct buffer.

17. The apparatus of claim 15 , wherein the instructions further cause the processor to: responsive to the software cache write operation failing to be issued to the software controlled cache since the last flush operation, skip the DMA get runtime coherency check; and, retrieve the data from memory into the direct buffer.

18. The apparatus of claim 15 , wherein the instructions further cause the processor to: responsive to the call being the DMA put operation, determine whether the software cache write operation has been issued to the software controlled cache for the data since the last flush operation; responsive to the software cache write operation being issued to the software controlled cache for the data since the last flush operation, perform a DMA put runtime coherency check between the direct buffer and the software controlled cache; and write the data from the direct buffer to the memory.

19. The apparatus of claim 18 , wherein the instructions to perform the DMA put runtime coherency check further cause the processor to: determine whether data that is to be written by the DMA put operation already exists in the software controlled cache; and responsive to the data existing in the software controlled cache, copy the data from the direct buffer into the software controlled cache.

20. The apparatus of claim 15 , wherein the instructions further cause the processor to responsive to the call being the DMA put operation, determine whether the software cache wrie operation has been issued to the software controlled cache for the data since the last flush operation; responsive to the software cache write operation failing to be issued to the software controlled cache for the data since the last flush operation, determine whether a software cache read operation has been issued to the software controlled cache for the data since the last flush operation; responsive to the software cache read operation being issued to the software controlled cache for the data since the last flush operation, determine whether the software cache read operation precedes the DMA put operation from the direct buffer to the memory; and responsive to the software cache read operation preceding the DMA put operation from the direct buffer to the memory, perform a DMA put runtime coherency check the direct buffer and the software controlled cache.