Processor for Performing Encryption Mask Processing Using Randomly Generated Instructions and Data

1. A processor comprising: a random instruction generating unit that generates a randomly generated instruction and data; a first operation unit that performs an encryption; and a second operation unit that performs a mask processing program by using the randomly generated instruction and the randomly generated data while the first operation unit performs the encryption, and performs a normal arithmetic operation while the first operation unit does not perform the encryption, wherein the random instruction generating unit, when the first operation unit performs the encryption, loads the randomly generated instruction into the second operation unit.

2. The processor according to claim 1 , wherein the second operation unit includes at least an arithmetic unit that has a same or reduced configuration as that of the first operation unit.

3. The processor according to claim 1 , further comprising: a memory unit that, when a mask processing program is performed by the second operation unit, only stores therein a result of the mask processing program performed by the second operation unit, and when the normal arithmetic operation is performed by the second operation unit, stores therein a result of arithmetic operation performed by the second operation unit.

4. The processor according to claim 3 , further comprising: a memory accessing unit that, when a memory is not accessed during the mask processing program, randomly accesses the memory unit.

5. The processor according to claim 1 , wherein the random instruction generating unit recognizes an execution phase of a computer program executed in the encryption from an execution history of the encryption, and if an operation frequency of the execution phase has changed during the encryption, loads an instruction by increasing or decreasing frequency of a random instruction into the second operation unit.

6. The processor according to claim 1 , further comprising: a power consumption measuring unit that measures power consumed by an entire arithmetic processing apparatus, wherein the random instruction generating unit, when a power consumption measured by the power consumption measuring unit is greater than a predetermined threshold, suppresses an instruction from being loaded into the second operation unit.

7. The processor according to claim 1 , further comprising: a clock phase control unit that controls a phase fluctuation of a clock provided in the second operation unit.

8. An arithmetic processing method for a processor including a first operation unit and a second operation unit, the arithmetic processing method comprising: generating a randomly generated instruction and data; performing a mask processing program by using the randomly generated instruction and the randomly generated data by the second operation unit while an encryption is performed by the first operation unit; and performing a normal arithmetic operation by the second operation unit while the encryption is not performed by the first operation unit, wherein the generating, when the first operation unit performs the encryption, includes loading the randomly generated instruction into the second operation unit.