Burst-Error Correction Methods and Apparatuses for Wireless Digital Communications Systems

1. A transmitter of a radio-frequency carrier wave modulated in amplitude responsive to 8-level digital symbols, which said 8-level digital symbols at selected times convey concatenated convolutional coding (CCC) of data that have previously been subjected to transverse Reed-Solomon (TRS) forward-error-correction (FEC) coding, said transmitter comprising: apparatus for generating successive bytes of TRS FEC coded data; an encoder connected for coding said successive bytes of said TRS-coded data with an error-locating code for the TRS FEC codewords, thereby generating a succession of codewords of said error-locating code; a de-interleaver connected for de-interleaving successive bits of said succession of said codewords of said error-locating code as converted to serial-bit format, thereby to generate a de-interleaver response in serial-bit format; an outer encoder connected for generating redundant outer convolutional coding of said de-interleaver response at one-half code rate; an interleaver connected for interleaving successive bit-pairs of said redundant outer convolutional coding, thereby to generate successive bit-pairs of an interleaver response wherein said successive bits of said succession of said codewords of said error-locating code as converted to serial-bit format are provided implied interleaving that preserves their original order; apparatus for time-division multiplexing said interleaver response with other digital signals to generate a time-division multiplex response; an inner encoder connected for generating redundant inner convolutional coding of said time-division multiplex response at two-thirds code rate; and symbol mapping apparatus connected for mapping said redundant inner convolutional coding to said 8-level digital symbols for modulating said radio-frequency carrier wave in amplitude.

2. The transmitter set forth in claim 1 , wherein said successive bit-pairs of said interleaver response as included in said time-division multiplex response each consist of a respective data bit followed by a respective parity bit, and wherein said inner encoder redundantly encodes said respective parity bits to implement serial concatenated convolutional coding (SCCC) for application to said symbol mapping apparatus as input signal.

3. The transmitter set forth in claim 2 , wherein the respective data bits of said successive bit-pairs of said interleaver response included in said SCCC applied to said symbol mapping apparatus are each mapped by said symbol mapping apparatus to a most significant one of the three bits defining a specific one of said 8-level digital symbols.

4. The transmitter set forth in claim 3 , including a Gray code to natural binary code remapper connected for Gray-code labeling said bit-pairs of said redundant outer convolutional coding before they reach said inner encoder connected for generating said redundant inner convolutional coding.

5. The transmitter set forth in claim 1 , wherein said successive bit-pairs of said interleaver response as included in said time-division multiplex response each consist of a respective data bit followed by a respective parity bit, and wherein said inner encoder redundantly encodes said respective data bits to implement parallel concatenated convolutional coding (PCCC) for application to said symbol mapping apparatus as input signal.

6. The transmitter set forth in claim 5 , wherein the respective parity bits of said successive bit-pairs of said interleaver response included in said SCCC applied to said symbol mapping apparatus are each mapped by said symbol mapping apparatus to a most significant one of the three bits defining a specific one of said 8-level digital symbols.

7. The transmitter set forth in claim 6 , including a Gray code to natural binary code remapper connected for Gray-code labeling said bit-pairs of said redundant outer convolutional coding before they reach said inner encoder connected for generating said redundant inner convolutional coding.

8. A receiver for radio-frequency carrier waves each modulated in amplitude responsive to a respective succession of 8-level digital symbols, said 8-level digital symbols of said respective succession at selected times conveying concatenated convolutional coding (CCC) of data that have previously been subjected to transverse Reed-Solomon (TRS) forward-error-correction (FEC) coding, said TRS-coded data having been subjected to implied symbol interleaving that preserves the original order of their successive bits within said CCC, said receiver comprising: apparatus for recovering soft CCC data descriptive of said 8-level digital symbols from a selected one of said radio-frequency carrier waves, said CCC data composed of triads of soft bits, the two less significant ones of the soft bits of each said triad conveying an inner convolutional coding component of said CCC, and the two more significant ones of the soft bits of each said triad conveying a symbol-interleaved outer convolutional coding component of said CCC, the one of the soft bits of each said triad of intermediate significance used in conveying both said inner convolutional coding component and said symbol-interleaved outer convolutional coding component of said CCC; a memory for temporarily storing said triads of soft bits; a first soft-input/soft-output (SISO) decoder connected for receiving the two less significant ones of the soft bits of each said triad conveying said inner convolutional coding component of said CCC and decoding said inner convolutional coding component of said CCC to generate a response supplying updates of said soft bits of intermediate significance in said triads as temporarily stored in said memory; a symbol de-interleaver having an input port connected for receiving from said memory 2-bit symbols of said symbol-interleaved outer convolutional coding component of said CCC composed of the most significant ones of the soft bits of said triads conveying said inner convolutional coding component of said CCC and corresponding updated ones of the soft bits of intermediate significance in said triads, said symbol de-interleaver connected for supplying from an output port thereof an outer convolutional coding component of said CCC as a symbol de-interleaver response; a second soft-input/soft-output (SISO) decoder connected for receiving said symbol de-interleaver response and decoding said outer convolutional coding component of said CCC therein to generate a response from said second SISO decoder that updates said soft bits of said outer convolutional coding component of said CCC; an interleaver connected for receiving at an input port thereof at least the less significant soft bits of said second SISO decoder response and for supplying an interleaved response from an output port of said interleaver; an extrinsic data processor connected for extracting extrinsic data in response to said interleaved response of said interleaver, said extrinsic data processor connected for supplying said extrinsic data to said first SISO decoder during turbo decoding cycles in a CCC decoding portion of said receiver, said CCC decoding portion of said receiver comprising the foreclaimed elements operable to supply from an output connection point soft decisions regarding said bits of said TRS-coded data in said original order; a hard-decision unit connected for receiving said soft decisions regarding said bits of said TRS-coded data from said output connection point in said CCC decoding portion of said receiver, said hard-decision unit further connected for supplying hard decisions regarding said bits of said TRS-coded data; and decoding apparatus for said TRS FEC coding connected for receiving said hard decisions regarding said bits of said TRS-coded data, said decoding apparatus for said TRS FEC coding decoding said hard decisions regarding bits of said TRS-coded data to generate corrected data for further processing.

9. The receiver set forth in claim 8 , wherein said output connection point in said CCC decoding portion of said receiver is at the output port of said interleaver.

10. The receiver set forth in claim 8 , wherein said output connection point in said CCC decoding portion of said receiver is at the input port of said symbol de-interleaver.

11. The receiver set forth in claim 8 , wherein said decoding apparatus for said TRS FEC coding is designed to use byte-error-location information to assist decoding procedures, and wherein said byte-error-location information is generated responsive to the confidence levels of said soft decisions regarding said bits of said TRS-coded data in said original order as supplied from said output connection point in said CCC decoding portion of said receiver at the output port of said interleaver.

12. The receiver set forth in claim 8 , said receiver further comprising: a binary-to-Gray-code re-mapper having an input port connected for receiving soft 2-bit symbols of said symbol-interleaved outer convolutional coding component of said CCC as supplied in updated form in the response of said first SISO decoder, said soft 2-bit symbols received at said input port of said binary-to-Gray-code re-mapper conveying updated symbol-interleaved outer convolutional coding component of said CCC in Gray-code-labeled natural-binary-code, an output port of said binary-to-Gray-code re-mapper connected for supplying said symbol de-interleaver with soft 2-bit symbols of said symbol-interleaved outer convolutional coding component of said CCC as re-mapped to Gray coding for de-interleaving; and a Gray-to-binary-code re-mapper in a cascade connection with said interleaver.

13. The receiver set forth in claim 12 , wherein said interleaver precedes said Gray-to-binary-code re-mapper in said cascade connection, wherein said second SISO decoder is operable for generating updated de-interleaved soft-2-bit symbols in said response from said second SISO decoder, wherein said second SISO decoder is connected for supplying said updated de-interleaved soft-2-bit symbols to said interleaver to be interleaved for generating an interleaver response composed of soft-2-bit symbols that include soft decisions regarding said bits of said TRS-coded data in said original order, and wherein said Gray-to-binary-code re-mapper is connected for responding to said interleaver response to supply said extrinsic data processor a Gray-to-binary-code re-mapper response.

14. The receiver set forth in claim 13 , wherein when receiving serial concatenated convolutional coding of TRS-coded data said Gray-to-binary-code re-mapper is connected for supplying said extrinsic data processor with said response of said Gray-to-binary-code re-mapper that is composed of more-significant soft data bits and less-significant further soft bits, said further soft bits expressing soft decisions as to the respective binary values of parity bits of interleaved outer convolutional coding as recoded from Gray code to natural binary code by said Gray-to-binary-code re-mapper.

15. The receiver set forth in claim 13 , wherein when parallel concatenated convolutional coding of TRS-coded data is being received said Gray-to-binary-code re-mapper is connected for supplying said extrinsic data processor just with soft data bits as recoded from Gray code to natural binary code.

16. The receiver set forth in claim 13 , wherein said second SISO decoder is connected for supplying its response as de-interleaved soft-2-bit symbols to said interleaver to be interleaved for generating an interleaver response composed of soft-2-bit symbols that include soft decisions regarding said bits of said TRS-coded data in said original order, wherein said output connection point in said CCC decoding portion of said receiver is at the output port of said interleaver, wherein said decoding apparatus for said TRS FEC coding is connected for exploiting byte-error-location information to assist its decoding procedures, and wherein said byte-error-location information is generated responsive to the confidence levels of said soft decisions regarding said bits of said TRS-coded data in said original order as supplied from said output connection point in said CCC decoding portion of said receiver at the output port of said interleaver.

17. The receiver set forth in claim 16 , further comprising: a confidence-level adjuster connected for receiving said interleaver response composed of soft-2-bit symbols, said confidence-level adjuster connected for supplying a response composed of soft-2-bit symbols to said Gray-to-binary-code re-mapper as input signal, said confidence-level adjuster connected for adjusting the confidence levels of the soft data bits included in said response thereof as compared to the confidence levels of the soft data bits included in said interleaver response, said adjusting of the confidence levels of the soft data bits being made by said confidence-level adjuster responsive to error-detection coding of said TRS-coded data.

18. The receiver set forth in claim 12 , wherein said output connection point in said CCC decoding portion of said receiver is at the input port of said symbol de-interleaver, wherein said decoding apparatus for said TRS FEC coding is designed to use byte-error-location information to assist decoding procedures, and wherein said byte-error-location information is generated responsive to the confidence levels of said soft decisions regarding said bits of said TRS-coded data in said original order as supplied from said output connection point in said CCC decoding portion of said receiver at the output port of said interleaver.

19. The receiver set forth in claim 18 , further comprising: a confidence-level adjuster connected for receiving said binary-to-Gray-code re-mapper response composed of soft-2-bit symbols of said symbol-interleaved outer convolutional coding component of said CCC as re-mapped to Gray coding, said confidence-level adjuster connected for supplying a response composed of soft-2-bit symbols to said symbol de-interleaver as input signal, said confidence-level adjuster connected for adjusting the confidence levels of the soft data bits included in said response thereof as compared to the confidence levels of the soft data bits included in said binary-to-Gray-code re-mapper response, said adjusting of the confidence levels of the soft data bits being made by said confidence-level adjuster responsive to error-detection coding of said TRS-coded data.