Oubit Based Systems, Devices, and Methods for Analog Processing

1. A system, comprising: a first qubit; a second qubit, wherein a portion of the first qubit crosses a portion of the second qubit substantially perpendicularly; and a coupler that has a perimeter and that provides a communicative coupling between the first qubit and the second qubit, the coupler physically proximate to the portion of the first qubit that crosses the portion of the second qubit.

2. The system of claim 1 wherein the perimeter of the 1 coupler encompasses at least a part of the portion of the first qubit that crosses the portion of the second qubit.

3. The system of claim 1 wherein the perimeter of the coupler encompasses a first portion of the first qubit that does not cross the second qubit and a second portion of the second qubit that does not cross the first qubit.

4. The system of claim 1 wherein the perimeter of the coupler comprises a first arm that extends substantially parallel to a length of the first qubit and a second arm that extends substantially parallel to a length of the second qubit.

5. The system of claim 1 wherein the first qubit includes a first qubit loop of superconducting material that is superconductive at a critical temperature and at least one Josephson junction, the second qubit includes a second qubit loop of superconducting material that is superconductive at a second temperature and at least one Josephson junction, and the coupler includes a coupling loop of superconducting material that is superconductive at a critical temperature.

6. The system of claim 5 wherein the coupling loop is interrupted by at least one Josephson junction.

7. The system of claim 5 wherein the coupler is on a separate layer from the first and the second qubits.

8. The system of claim 5 wherein the coupler is on a same layer as one of the first or the second qubits.

9. The system of claim 1 wherein the coupler is operable to at least one of ferromagnetically, anti-ferromagnetically and transversely couple the first qubit and the second qubit.

10. A multi-layered computer chip, comprising: a first plurality N of qubits laid out at least partially in a first metal layer; a second plurality M of qubits laid out at least partially in a second metal layer; each of the qubits of the second plurality of qubits cross each of the qubits of the first plurality of qubits; and a first plurality N times M of coupling devices, each of the coupling devices proximate to where a respective pair of the qubits from the first and the second plurality of qubits cross each other.

11. The multi-layered computer chip of claim 10 wherein at least of the coupling devices comprises a first arm extending substantially parallel to a length of a qubit of the first plurality of N qubits and a second arm extending substantially parallel to a length a second qubit of the second plurality of M qubits.

12. The multi-layered computer chip of claim 10 wherein the plurality of coupling devices are laid out at least partially in the second metal layer.

13. The multi-layered computer chip of claim 10 wherein M is equal to N.

14. The multi-layered computer chip of claim 10 , further comprising: a metal shielding layer positioned to reduce magnetic noise around the qubits and the couplers.

15. The multi-layered computer chip of claim 10 wherein the second plurality of qubits is laid out in both the second metal layer and the first metal layer and a plurality of vias provide respective current paths between the second and the first metal layers.

16. The multi-layered computer chip of claim 10 wherein the plurality of coupling devices is laid out in both the second metal layer and the first metal layer and a plurality of vias provide respective current paths between the second and the first metal layers.

17. The multi-layered computer chip of claim 10 wherein the qubits of the first plurality of qubits are arranged parallel to one another, the qubits of the second plurality of qubits are arranged parallel to one another, and the qubits of the second plurality of qubits are arranged perpendicularly with respect to the qubits of the first plurality of qubits.

18. The multi-layered computer chip of claim 10 , further comprising: a superconducting probe card to establish an interface between the multi-layered computer chip and a digital computer, the superconducting probe card comprising: a printed circuit board including a dielectric medium that carries at least a first conductive trace, wherein the first conductive trace is formed by a material that is superconducting below a critical temperature; and at least a first conductive needle that is at least partially formed by a material that is superconducting below a critical temperature, wherein a first end of the first conductive needle is communicably coupled to the first conductive trace on the printed circuit board and a second end of the first conductive needle is tapered to form a point; wherein the critical temperature of the first conductive trace and the critical temperature of the first conductive needle are both approximately equal to or greater than an operating temperature of the superconducting probe card.

19. The multi-layered computer chip of claim 10 wherein the qubits of the first plurality of qubits are arranged in a consecutive order from a first to an n th qubit, the qubits of the second plurality of qubits are arranged in a consecutive order from a first qubit to an m th qubit, the first qubit of the first plurality of qubits is ferromagnetically coupled to the first qubit of the second plurality of qubits, a second qubit of the first plurality of qubits is ferromagnetically coupled to a second qubit of the second plurality of qubits, a third qubit of the first plurality of qubits is ferromagnetically coupled to a third qubit of the second plurality of qubits, a fourth qubit of the first plurality of qubits is ferromagnetically coupled to a fourth qubit of the second plurality of qubits, the first qubit of the first plurality of qubits is controllably coupleable to each of the second, the third and the fourth qubits of the second plurality of qubits, the second qubit of the first plurality of qubits is controllably coupleable to each of the first, the third and the fourth qubits of the second plurality of qubits, the third qubit of the first plurality of qubits is controllably coupleable to each of the first, the second, and the fourth qubits of the second plurality of qubits, and the fourth qubit of the first plurality of qubits is controllably coupleable to each of the first, the second, and the third qubits of the second plurality of qubits to form a first K 4 block.

20. The multi-layered computer chip of claim 19 , further comprising: a third plurality I of qubits laid out in a first metal layer; a fourth plurality J of qubits laid out at least partially in a second metal layer; each of the qubits of the second plurality of qubits cross each of the qubits of the first plurality of qubits; a fifth plurality K of qubits laid out in a first metal layer; a sixth plurality L of qubits laid out at least partially in a second metal layer; each of the qubits of the second plurality of qubits cross each of the qubits of the first plurality of qubits; a second plurality I times J of coupling devices, each of the coupling devices of the second plurality of coupling devices at least partially encompassing an area where a respective pair of the qubits from the third and the fourth plurality of qubits cross each other, wherein the qubits of the third plurality of qubits are arranged in a consecutive order from a first to an nth qubit, the qubits of the fourth plurality of qubits are arranged in a consecutive order from a first qubit to an nth qubit, the first qubit of the third plurality of qubits is controllably coupleable to each of the first, the second, the third and the fourth qubits of the fourth plurality of qubits, the second qubit of the third plurality of qubits is controllably coupleable to each of the first, the second, the third and the fourth qubits of the fourth plurality of qubits, the third qubit of the third plurality of qubits is controllably coupleable to each of the first, the second, the third, and the fourth qubits of the fourth plurality of qubits, and the fourth qubit of the third plurality of qubits is controllably coupleable to each of the first, the second, the third, and the fourth qubits of the fourth plurality of qubits to form a first bipartite block; and a third plurality K times L of coupling devices, each of the coupling devices of the second plurality of coupling devices at least partially encompassing an area where a respective pair of the qubits from the third and the fourth plurality of qubits cross each other, wherein the qubits of the fifth plurality of qubits are arranged in a consecutive order from a first to an nth qubit, the qubits of the sixth plurality of qubits are arranged in a consecutive order from a first qubit to an nth qubit, the first qubit of the fifth plurality of qubits is ferromagnetically coupled to the first qubit of the sixth plurality of qubits, a second qubit of the fifth plurality of qubits is ferromagnetically coupled to a second qubit of the sixth plurality of qubits, a third qubit of the fifth plurality of qubits is ferromagnetically coupled to a third qubit of the sixth plurality of qubits, a fourth qubit of the fifth plurality of qubits is ferromagnetically coupled to a fourth qubit of the sixth plurality of qubits, the first qubit of the fifth plurality of qubits is controllably coupleable to each of the second, the third and the fourth qubits of the sixth plurality of qubits, the second qubit of the fifth plurality of qubits is controllably coupleable to each of the first, the third and the fourth qubits of the sixth plurality of qubits, the third qubit of the fifth plurality of qubits is controllably coupleable to each of the first, the second, and the fourth qubits of the sixth plurality of qubits, and the fourth qubit of the fifth plurality of qubits is controllably coupleable to each of the first, the second, and the third qubits of the sixth plurality of qubits to form a second K 4 block, and wherein the qubits of the third plurality of qubits are ferromagnetically coupled with respective ones of the qubits of the first plurality of qubits and wherein the qubits from the fourth plurality of qubits are ferromagnetically coupled with respective ones of the qubits of the sixth plurality of qubits to form a first K 8 block.

21. The multi-layered computer chip of claim 20 , further comprising: an additional plurality of qubits and an additional plurality of couplers configured to form a second K 8 block, wherein at least one qubit from the first K 8 block is controllably coupled to at least one qubit from the second K 8 block.

22. The multi-layered computer chip of claim 20 wherein at least one of the couplers is a corner coupler that is operable to couple at least one qubit from the first K 4 block to a corresponding respective qubit from the either the fifth or the sixth plurality of qubits.

23. A system, comprising: a first qubit; a second qubit, wherein a portion of the first qubit crosses a portion of the second qubit; and a coupler that has a perimeter and that provides a communicative coupling between the first qubit and the second qubit, the coupler physically proximate to the portion of the first qubit that crosses the portion of the second qubit, wherein the first qubit includes a first qubit loop of superconducting material that is superconductive at a critical temperature and at least one Josephson junction, the second qubit includes a second qubit loop of superconducting material that is superconductive at a critical temperature and at least one Josephson junction, and the coupler includes a coupling loop of superconducting material that is superconductive at a critical temperature.

24. The system of claim 23 wherein the portion of the first qubit crosses the portion of the second qubit substantially perpendicularly.

25. The system of claim 23 wherein the perimeter of the coupler encompasses at least a part of the portion of the first qubit that crosses the portion of the second qubit.

26. The system of claim 23 wherein the perimeter of the coupler encompasses a first portion of the first qubit that does not cross the second qubit and a second portion of the second qubit that does not cross the first qubit.

27. The system of claim 23 wherein the perimeter of the coupler comprises a first arm that extends substantially parallel to a length of the first qubit and a second arm that extends substantially parallel to a length of the second qubit.

28. The system of claim 23 wherein the coupling loop is interrupted by at least one Josephson junction.

29. The system of claim 23 wherein the coupler is on a separate layer from the first and the second qubits.

30. The system of claim 23 wherein the coupler is on a same layer as one of the first or the second qubits.

31. The system of claim 23 wherein the coupler is operable to at least one of ferromagnetically, anti-ferromagnetically and transversely couple the first qubit and the second qubit.