Memory Controller and Device with Data Strobe Calibration

1. A memory controlling method, comprising: receiving and passing a data signal via a DQ path for outputting a delayed data signal; receiving and passing a data strobe signal via a DQS path; generating a compensated data strobe signal having a calibrated latency from the data strobe signal, wherein the calibrated latency is determined by an adjustment signal; sampling the delayed data signal by the compensated data strobe signal to generate an output data; generating the adjustment signal according to the output data; performing a calibration to adjust the adjustment signal for adjusting the calibrated latency.

2. The memory controlling method of claim 1 , wherein the adjustment signal is adjusted by determining a maximum and a minimum value of the calibrated latency that allows the delayed data signal to be sampled correctly and the calibrated latency is generated by receiving the adjustment signal, the calibrated latency corresponding to an average of the maximum and minimum values.

3. The memory controlling method of claim 1 , further comprising: initializing the calibration by delivering a refresh command, wherein: when the refresh command is delivered, a calibration mode is initialized synchronously with an auto refresh operation; in the calibration mode: the data signal and data strobe signal are input, wherein the data signal comprises a calibration pattern; sending an adjustment signal for delaying the data strobe signal for a calibrated latency to generate a compensated data strobe signal; sampling the delayed data signal based on the compensated data strobe signal for generating the output data; and adjusting the adjustment signal based on the output data and the calibration pattern.

4. The memory controlling method of claim 3 , further comprising: providing the adjustment signal for controlling the calibrated latency; and initializing the calibration by delivering an enable signal to enabling the step of controlling the calibrated latency; and comparing the output data with the calibration pattern to adjust the adjustment signal when the enable signal is delivered.

5. The memory controlling method of claim 1 , further comprising: delivering commands to control a memory device, wherein: initializing the calibration by delivering an enable signal; initializing a calibration mode when the enable signal is delivered; sending an interrupt command to interrupt the memory device when the enable signal is delivered; in the calibration mode: generating a calibration pattern as a data signal; delaying the data signal to generate a delayed data signal; sending an adjustment signal to delay the data strobe signal so that a compensated data strobe signal having a calibrated latency; sampling the delayed data signal based on the compensated data strobe signal for generating the output data; and adjusting the adjustment signal according to the output data and the calibration pattern.

6. The memory controlling method of claim 5 , further comprising: providing the adjustment signal to control the latency difference between the delayed data signal and the compensated data strobe signal; sending an enable signal to initializing the calibration; providing the calibration pattern wherein: sending the calibration pattern as a data signal when the calibration is initialized; and comparing the output data with the calibration pattern to determine the validity of the adjustment signal.

7. The memory controlling method of claim 5 , further comprising: providing the adjustment signal to control the calibrated latency; sending an enable signal to initialize the calibration; and providing the calibration pattern, wherein: issuing a write command to the memory device when the calibration is initialized; writing the calibration pattern as a data signal to the memory device; issuing a read command to read the data signal and the data strobe signal from the memory device; and comparing the output data with the calibration pattern to determine the validity of the adjustment signal.

8. The memory controlling method of claim 7 , further comprising: storing a maximum value and a minimum value; generating the adjustment signal from the maximum value or the minimum value; comparing the output data with the calibration patter; and determine whether the output data matches the calibration patter when receiving the enable signal; and updating the maximum value or the minimum value when the calibration; wherein when the calibration is finished, the adjustment signal is set to an average of the maximum and minimum values.

9. The memory controlling method of claim 7 , further comprising: preserving data corresponding to a specific address in the memory device before writing the data signal comprising the calibration pattern to the memory device; multiplexing the calibration pattern and the preserved data; providing a trigger signal every predetermined period; generating the enable signal to initialize the calibration when receiving the trigger signal; wherein: in the calibration mode, outputting the calibration pattern as the data signal; and when the calibration is finished, restoring the preserved data to the memory device.