System and Method for Automatically Managing Clock Relationships in Integrated Circuit Designs

1. A computer-implemented method for identifying and managing the relationships between clock domains in an integrated circuit design, comprising: receiving at a computer system as inputs a description of the design, and definitions of clock waveforms and timing constraints used in the design; and in the computer system, automatically identifying pairs of clocks from the timing constraints and, for each identified pair of clocks: in the computer system, categorizing each clock in the pair as a source clock or a generated clock and, if the clock is a generated clock, its parent clock; in the computer system, identifying any points in the design at which the clocks in the pair of clocks are applied simultaneously; in the computer system, identifying any points in the design at which the clocks in the pair of clocks logically merge; in the computer system, if the clocks in the pair of clocks are both source clocks, determining the default relationship between the clocks; in the computer system, if either clock in the pair of clocks is a generated clock, determining the relationship between the generated clock and the source clock from which the generated clock is derived; in the computer system, if either clock in the pair of clocks is a generated clock, determining whether the generated clock inherits any relationship from its parent clock; and in the computer system, assigning the clock pair to one of a plurality of behavioral categories based upon one of the determined relationships.

2. The computer-implemented method of claim 1 wherein identifying the relationships between all of the clocks further comprises identifying each possible pair of clocks and categorizing the relationship of each such clock pair.

3. The computer-implemented method of claim 1 wherein identifying any points in the design at which a plurality of clock definitions logically merge further comprises determining in the computer system: whether there are common objects reached by signals from both clocks; whether there are unique objects reached by signals from one clock or the other; and whether there are circuit paths between common objects, between common objects and the unique objects of either clock, and/or between the unique objects of one clock and the unique objects of the other clock.

4. The computer-implemented method of claim 1 wherein determining the relationships between source clocks further comprises assuming that all source clocks are asynchronous to one another.

5. The computer-implemented method of claim 1 wherein determining the relationships between source clocks further comprises assuming that all source clocks with a common frequency are synchronous to one another.

6. The computer-implemented method of claim 5 wherein determining the relationships between source clocks further comprises assuming that all source clocks that do not have a common frequency are asynchronous to one another.

7. The computer-implemented method of claim 1 wherein determining the relationships between source clocks and generated clocks further comprises assuming that a generated clock is synchronous to a source clocks from which it is derived unless the design description specifies that they are asynchronous or the generated clock logically merges with the source clock.

8. The computer implemented method of claim 1 , further comprising receiving in the computer system as an input a list of timing exceptions.

9. The computer implemented method of claim 1 , further comprising verifying in the computer system any timing exceptions between the clocks specified in the description, based on the behavioral category in which each clock is categorized.

10. The computer implemented method of claim 1 , further comprising creating in the computer system any missing timing exceptions between the clocks specified in the description, based on the behavioral category in which each clock is categorized.

11. The computer-implemented method of claim 1 wherein the description of the design is in a synthesizable format.

12. The computer-implemented method of claim 1 wherein the description of the design is in synthesizable RTL-level format.

13. The computer-implemented method of claim 1 wherein the description of design is a synthesized gate-level netlist.

14. The computer-implemented method of claim 1 wherein the definitions of clock waveforms and timing constraints are in SDC format.

15. A system for identifying and managing the relationships between clock domains in an integrated circuit design, comprising: input means receiving a description of the design, and definitions of all clock waveforms and timing constraints used in the design; and a processor configured to automatically identify pairs of clocks from the timing constraints; and, for each identified pair of clocks: categorize each clock in the pair as a source clock or a generated clock and, if the clock is a generated clock, its parent clock; identify any points in the design at which the clocks in the pair of clocks are applied simultaneously; identify any points in the design at which the clocks in the pair of clocks logically merge; if the clocks in the pair of clocks are both source clocks, determine the default relationship between the clocks; if either clock in the pair of clocks is a generated clock, determine the relationship between the generated clock and the source clock from which the generated clock is derived; if either clock in the pair of clocks is a generated clock, determine whether the generated clock inherits any relationship from its parent clock; and assign the clock pair to one of a plurality of behavioral categories based upon one of the determined relationships.

16. A non-transitory computer readable medium having embodied thereon a program, the program being executable by a processor to perform a method of identifying and managing the relationships between clock domains in an integrated circuit design, the method comprising the steps of: receiving at a computer system as inputs a description of the design, and definitions of clock waveforms and timing constraints used in the design; and in the computer system, automatically identifying pairs of clocks from the timing constraints and, for each identified pair of clocks: in the computer system, categorizing each clock in the pair as a source clock or a generated clock and, if the clock is a generated clock, its parent clock; in the computer system, identifying any points in the design at which the clocks in the pair of clocks are applied simultaneously; in the computer system, identifying any points in the design at which the clocks in the pair of clocks logically merge; in the computer system, if the clocks in the pair of clocks are both source clocks, determining the default relationship between the clocks; in the computer system, if either clock in the pair of clocks is a generated clock, determining the relationship between the generated clock and the source clock from which the generated clock is derived; in the computer system, if either clock in the pair of clocks is a generated clock, determining whether the generated clock inherits any relationship from its parent clock; and in the computer system, assigning the clock pair to one of a plurality of behavioral categories based upon one of the determined relationships.

17. The method of claim 1 , wherein categorizing each clock in the pair as a source clock or a generated clock, and, if the clock is a generated clock, its parent clock further comprises categorizing each clock in the pair as a source clock, a generated clock or a virtual clock, and further comprising: in the computer system, if either clock, is a virtual clock, determining any relationship between the virtual clock and an associated source clock or generated clock in the integrated circuit design and storing the determined relationship of the virtual clock to an associated clock in a database.

18. The non-transitory computer readable medium of claim 16 , wherein the step of categorizing each clock in the pair as a source clock or a generated clock, and, if the clock is a generated clock, its parent clock further comprises categorizing each clock in the pair as a source clock, a generated clock or a virtual clock, and the method further comprises the step of: in the computer system, if either clock is a virtual clock, determining any relationship between the virtual clock and an associated source clock or generated clock in the integrated circuit design and storing the determined relationship of the virtual clock to an associated clock in a database.

19. The non-transitory computer readable medium of claim 16 , wherein the method further comprises the steps of identifying any points in the design at which a plurality of clock definitions logically merge further comprises determining in the computer system: whether there are common objects reached by signals from both clocks; whether there are unique objects reached by signals from one clock or the other; and whether there are circuit paths between common objects, between common objects and the unique objects of either clock, and/or between the unique objects of one clock and the unique objects of the other clock.

20. The non-transitory computer readable medium of claim 16 , wherein the method further comprises the step of creating in the computer system any missing timing exceptions between the clocks specified in the description, based on the behavioral category in which each clock is categorized.