Coprocessor Interface Architecture and Methods of Operating the Same

1. A system, comprising: a bus; a processor circuit coupled to the bus; a memory circuit; a multi-channel memory controller coupled between the bus and the memory circuit; and a first coprocessor coupled to the processor circuit, the first coprocessor further being coupled to the multi-channel memory controller via a first interface that bypasses the processor circuit and the bus, wherein the memory controller comprises an address generator circuit that calculates a series of sequential addresses for the memory circuit in response to data received from the coprocessor specifying a sequential access pattern, and that calculates a series of non-sequential addresses for the memory circuit in response to data received from the coprocessor specifying a non-sequential access pattern.

2. The system of claim 1 , wherein: the system comprises an integrated circuit (IC) that includes the processor circuit, the memory circuit, the multi-channel memory controller, and the first coprocessor; and the bus comprises an on-chip peripheral bus of the IC.

3. The system of claim 1 , wherein: the system comprises an integrated circuit (IC) that includes the memory circuit, the multi-channel memory controller, the first coprocessor, and the bus; and the processor circuit is implemented in a separate physical structure not included in the IC.

4. The system of claim 1 , further comprising: a second coprocessor coupled to the processor circuit, the second coprocessor further being coupled to the multi-channel memory controller via a second interface that bypasses the processor circuit and the bus.

5. The system of claim 1 , wherein: the first coprocessor is coupled to the processor circuit via a first serial interface; and the first coprocessor is coupled to the multi-channel memory controller via a second serial interface.

6. The system of claim 1 , wherein the processor circuit comprises a microprocessor.

7. The system of claim 6 , wherein the system comprises a programmable logic device (PLD), and the processor circuit comprises a microprocessor included as hard-coded logic in the PLD.

8. The system of claim 6 , wherein the system comprises a programmable logic device (PLD), and the processor circuit comprises a microprocessor implemented using programmable logic elements of the PLD.

9. The system of claim 1 , wherein the address generator circuit is coupled between the coprocessor and the multi-channel memory controller, the first interface traversing the address generator circuit.

10. The system of claim 1 , wherein the address generator circuit calculates a series of linear addresses for the memory circuit in response to data received from the coprocessor specifying a linear access pattern and calculates a series of non-linear addresses for the memory circuit in response to data received from the coprocessor specifying a non-linear access pattern.

11. A method of operating a coprocessing system, wherein the system comprises a first processor circuit, a second processor circuit, a memory controller, and a memory circuit, the method comprising: sending a command and an access pattern from the first processor circuit to the memory controller via a first communications link; decoding the access pattern in the memory controller to produce a series of addresses corresponding to locations in the memory circuit; wherein the series of addresses produced comprises a series of sequential addresses in response to the access pattern received from the first processor circuit specifying a sequential access pattern, and the series of addresses produced comprises a series of non-sequential addresses in response to the access pattern received from the first processor circuit specifying a non-sequential access pattern; sending a series of read requests from the memory controller to the memory circuit and fetching in response a stream of data from the memory circuit at the locations corresponding to the series of addresses; and providing the stream of data from the memory controller to the second processor circuit via a second communications link independent from the first communications link, the stream of data bypassing the first processor circuit.

12. The method of claim 11 , wherein the first processor circuit comprises a main processor, and the second processor circuit comprises a coprocessor.

13. The method of claim 11 , wherein the first processor circuit comprises a first coprocessor, and the second processor circuit comprises a second coprocessor.

14. The method of claim 11 , wherein the series of addresses produced comprises a series of linear addresses in response to the access pattern received from the first processor circuit specifying a linear access pattern, and the series of addresses produced comprises a series of non-linear addresses in response to the access pattern received from the first processor circuit specifying a non-linear access pattern.

15. A method of operating a coprocessing system, wherein the system comprises a first processor circuit, a second processor circuit, a memory controller, and a memory circuit, the method comprising: sending a command and an access pattern from the first processor circuit to the memory controller via a first communications link; sending a stream of data from the second processor circuit to the memory controller via a second communications link independent from the first communications link; decoding the access pattern in the memory controller to produce a series of addresses corresponding to locations in the memory circuit; wherein the series of addresses produced comprises a series of sequential addresses in response to the access pattern received from the first processor circuit specifying a sequential access pattern, and the series of addresses produced comprises a series of non-sequential addresses in response to the access pattern received from the first processor circuit specifying a non-sequential access pattern; and sending a series of data write requests from the memory controller to the memory circuit and writing the stream of data to the locations in the memory circuit corresponding to the series of addresses, the stream of data bypassing the first processor circuit.

16. The method of claim 15 , wherein the first processor circuit comprises a main processor, and the second processor circuit comprises a coprocessor.

17. The method of claim 15 , wherein the first processor circuit comprises a first coprocessor, and the second processor circuit comprises a second coprocessor.

18. The method of claim 15 , wherein the series of addresses produced comprises a series of linear addresses in response to the access pattern received from the first processor circuit specifying a linear access pattern, and the series of addresses produced comprises a series of non-linear addresses in response to the access pattern received from the first processor circuit specifying a non-linear access pattern.