Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Personal Computer System

1. An apparatus comprising: an adapter adapted on a single semiconductor die to communicate with a processor according to a first protocol and to communicate with an interface according to a second protocol; the interface adapted on the single semiconductor die and coupled to the adapter, the interface to perform common functionality for a plurality of heterogeneous resources coupled to an interconnect; and the interconnect adapted on the single semiconductor die to couple the interface to the plurality of heterogeneous resources adapted on the single semiconductor die, each including an intellectual property (IP) core and a shim, wherein the shim is to implement a header for the IP core, the apparatus to operate according to the first protocol and the IP core to operate according to the second protocol.

2. The apparatus of claim 1 , wherein the interface is to translate configuration cycles of the first protocol into a format for the second protocol, wherein the first protocol corresponds to a peripheral component interconnect (PCI) protocol.

3. The apparatus of claim 2 , wherein the interface is to perform address translation to translate a re-locatable PCI address into an advanced extensible interface (AXI)/open core protocol (OCP) address.

4. The apparatus of claim 1 , wherein the interface is to perform operations that are common across the plurality of heterogeneous resources, and each shim is to perform operations that are specific to the corresponding IP core.

5. The apparatus of claim 4 , wherein the common operations include address translation and ordering of transactions received from the processor, and the specific operations include power management and error handling.

6. The apparatus of claim 5 , wherein the ordering is to satisfy a producer-consumer model of the first protocol.

7. The apparatus of claim 1 , wherein the interconnect comprises an auto-generated interconnect fabric.

8. The apparatus of claim 2 , wherein the interface is to route accesses to the header to a corresponding shim, and the shim is to implement the header for the corresponding IP core, wherein the interface is to further route accesses to a device memory space to the corresponding shim.

9. The apparatus of claim 8 , wherein the corresponding shim is to consume read-write operations to the header and to communicate other transactions to the corresponding IP core.

10. A system-on-chip (SoC) comprising: a processor adapted on a semiconductor die; a host interface adapted on the semiconductor die coupled to the processor, the host interface to couple the processor to a memory and an adapter; the adapter coupled to the host interface to communicate with the host interface according to a first protocol and to communicate with a second interface according to a second protocol; the second interface adapted on the semiconductor die coupled to the adapter, the second interface to perform common functionality for a plurality of heterogeneous resources coupled to an interconnect; and the interconnect adapted on the semiconductor die to couple the second interface to the plurality of heterogeneous resources, each of the plurality of heterogeneous resources including a core and a shim, wherein the SoC is to operate according to the first protocol and the core is to operate according to the second protocol.

11. The SoC of claim 10 , further comprising a system comprising an ultra mobile system, wherein the processor is to execute a PC operating system using the first protocol.

12. The SoC of claim 11 , wherein the second interface is to translate configuration cycles from the processor into a format for the second protocol, wherein the first protocol corresponds to a peripheral component interconnect (PCI) protocol and the second interface is to perform address translation to translate a re-locatable PCI address into an open core protocol (OCP) address.

13. The SoC of claim 12 , wherein each shim is to perform operations that are specific to the corresponding core, the common operations including the address translation and ordering of transactions received from the processor, and the specific operations including power management and error handling.

14. The SoC of claim 10 , wherein the second interface includes an address redirection table.

15. An apparatus comprising: an adapter to communicate with a first component according to a peripheral component interconnect (PCI)-compatible protocol and to communicate with a first interface according to a second protocol; the first interface coupled to the adapter, the first interface to perform address translation and ordering of transactions received from the first component, wherein the first interface is to translate configuration cycles of the PCI-compatible protocol into a format for the second protocol; and an interconnect to couple the first interface to a plurality of heterogeneous resources, each of the plurality of heterogeneous resources including a core and a shim, wherein the apparatus is to operate according to the PCI-compatible protocol and the core is to operate according to the second protocol.

16. The apparatus of claim 15 , wherein the first interface is to perform the address translation to translate a re-locatable address into a fixed address.

17. The apparatus of claim 15 , wherein the first interface is to perform operations that are common across the plurality of heterogeneous resources, and each shim is to perform operations that are specific to the corresponding core.

18. The apparatus of claim 15 , wherein the first component comprises a processor coupled to the adapter via a direct media interface bus.

19. The apparatus of claim 15 , wherein the corresponding shim is to consume read-write operations to a PCI header for the core and to communicate other transactions to the corresponding core.

20. The apparatus of claim 15 , wherein at least one of the plurality of heterogeneous resources is an intellectual property block of a third party.