Configurable Memory Device

1. A configurable memory device comprising: a substrate; an array of non-volatile memory cells including at least one non-volatile memory cell on the substrate; an array of volatile memory cells including at least one volatile memory cell on the substrate; an interface configured to enable coupling of the memory device to a memory controller associated therewith, the interface comprising an address translation logic configured to be programmed through a set of registers associated therewith to enable configurable mapping of different sectors of the memory device to different memory address space locations in a computing system associated with the memory device; a tag register associated with the array of volatile memory cells to track a data update associated therewith; and a hybrid memory on the substrate formed through programming a portion of the array of non-volatile memory cells to have a same address as a portion of the array of volatile memory cells, wherein the hybrid memory is configured to be non-volatile and to enable random access of data therein.

2. The configurable memory device of claim 1 , wherein the array of non-volatile memory cells is an array of one of Read-Only Memory (ROM) cells and Flash memory cells, and wherein the array of volatile memory cells is an array of Random Access Memory (RAM) cells.

3. The configurable memory device of claim 1 , wherein the memory controller is configured to enable access to at least one of the array of non-volatile memory cells, the array of volatile memory cells and the hybrid memory.

4. The configurable memory device of claim 3 , wherein the memory controller is configured to enable at least one of: a memory read operation from one of the array of non-volatile memory cells, the array of volatile memory cells and the hybrid memory; an erase operation on one of the array of non-volatile memory cells and a non-volatile portion of the hybrid memory; a memory write operation to the one of the array of non-volatile memory cells, the array of volatile memory cells and the hybrid memory; a transfer operation signifying copying data from a volatile portion of the hybrid memory to a non-volatile portion therein; a recall operation signifying one of copying data from the non-volatile portion of the hybrid memory to the volatile portion therein and copying data from a portion of the array of non-volatile memory cells not including any portion of the hybrid memory to another portion therein through a buffer associated therewith; a register read operation through the memory device to allow reading of registers associated with the memory device, the registers including at least the set of registers associated with the address translation logic; and a register write operation through the memory device to allow writing to the registers associated with the memory device through transmission of an operation code associated with an appropriate type of access of the memory device thereto, the appropriate type of access indicating the corresponding one of the memory read operation, the erase operation, the memory write operation, the transfer operation, the recall operation, the register read operation, and the register write operation.

5. The configurable memory device of claim 4 , wherein the memory controller is configured to drive an enable signal to an appropriate level to initiate transmission of the operation code, and wherein one of a rising edge and a falling edge of a clock associated with the interface configured to enable coupling of the memory device to the memory controller is utilized to time the corresponding one of the memory read operation, the erase operation, the memory write operation, the transfer operation, the recall operation, the register read operation and the register write operation.

6. The configurable memory device of claim 5 , wherein the erase operation includes one of an erase memory operation configured to erase all content associated with the one of the array of non-volatile memory cells and the non-volatile portion of the hybrid memory, an erase sector operation configured to erase all content associated with a sector of the one of the array of non-volatile memory cells and the non-volatile portion of the hybrid memory, and an erase page operation configured to erase all content associated with a page of the sector of the one of the array of non-volatile memory cells and the non-volatile portion of the hybrid memory.

7. The configurable memory device of claim 5 , wherein the address translation logic comprises: an address map register configured to store an address associated with a corresponding sector of the one of the array of non-volatile memory cells, the array of volatile memory cells and the hybrid memory; and a comparator, associated with the address map register and configured to compare a memory access address associated with the corresponding one of the memory read operation, the erase operation, the memory write operation, the transfer operation and the recall operation with the address stored in the address map register to enable an appropriate memory access associated therewith.

8. The configurable memory device of claim 7 , wherein the transfer operation between the volatile portion of the hybrid memory and the non-volatile portion therein is performed sequentially, wherein the sequential transfer operation signifies performing the transfer operation one modified memory page at a time, wherein the modified memory page signifies a page associated with a corresponding sector of the hybrid memory including data that has been modified following a previous transfer operation associated therewith, wherein the tag register includes a tag bit associated with the modified memory page, and wherein the tag bit associated with the modified memory page indicates the modified status thereof.

9. The configurable memory device of claim 7 , wherein the recall operation between the one of the non-volatile portion of the hybrid memory and the volatile portion therein and the portion of the array of non-volatile memory cells not including any portion of the hybrid memory and the another portion therein is sequentially performed one memory page at a time.

10. A computing system comprising: a memory device comprising: a substrate; an array of non-volatile memory cells including at least one non-volatile memory cell on the substrate; an array of volatile memory cells including at least one volatile memory cell on the substrate; and an interface comprising an address translation logic configured to be programmed through a set of registers associated therewith to enable configurable mapping of different sectors of the memory device to different memory address space locations in the computing system; and a memory controller, associated with the memory device and coupled to the memory device through the interface, wherein the memory device further comprises a hybrid memory on the substrate formed through programming a portion of the array of non-volatile memory cells to have a same address as a portion of the array of volatile memory cells, wherein the hybrid memory is configured to be non-volatile and to enable random access of data therein, wherein the memory device further comprises a hybrid memory on the substrate formed through programming a portion of the array of non-volatile memory cells to have a same address as a portion of the array of volatile memory cells, wherein the hybrid memory is configured to be non-volatile and to enable random access of data therein.

11. The computing system of claim 10 , wherein the array of non-volatile memory cells is an array of one of Read-Only Memory (ROM) cells and Flash memory cells, and wherein the array of volatile memory cells is an array of Random Access Memory (RAM) cells.

12. The computing system of claim 10 , wherein the memory device is a System-on-a-Chip (SoC).

13. The computing system of claim 10 , wherein the interface of the memory device configured to enable coupling of the memory controller therewith utilizes one of a serial bus and a parallel bus therefor.

14. The computing system of claim 10 , wherein the memory controller is configured to enable at least one of: a memory read operation from one of the array of non-volatile memory cells, the array of volatile memory cells and the hybrid memory; an erase operation on one of the array of non-volatile memory cells and a non-volatile portion of the hybrid memory; a memory write operation to the one of the array of non-volatile memory cells, the array of volatile memory cells and the hybrid memory; a transfer operation signifying copying data from a volatile portion of the hybrid memory to a non-volatile portion therein; a recall operation signifying one of copying data from the non-volatile portion of the hybrid memory to the volatile portion therein and copying data from a portion of the array of non-volatile memory cells not including any portion of the hybrid memory to another portion therein through a buffer associated therewith; a register read operation through the memory device to allow reading of registers associated with the memory device, the registers including at least the set of registers associated with the address translation logic; and a register write operation through the memory device to allow writing to the registers associated with the memory device through transmission of an operation code associated with an appropriate type of access of the memory device thereto, the appropriate type of access indicating the corresponding one of the memory read operation, the erase operation, the memory write operation, the transfer operation, the recall operation, the register read operation, and the register write operation.

15. A method comprising: forming a memory device through providing an array of non-volatile memory cells including at least one non-volatile memory cell and an array of volatile memory cells including at least one volatile memory cell on a substrate; appropriately programming an address translation logic associated with the memory device through a set of registers associated therewith to enable configurable mapping of different sectors of the memory device to different memory address space locations in a computing system associated with the memory device; tracking a data update associated with the array of volatile memory cells through a tag register associated therewith; and forming a hybrid memory on the substrate through programming a portion of the array of non-volatile memory cells to have a same address as a portion of the array of volatile memory cells, the hybrid memory being configured to be non-volatile and to enable random access of data therein, wherein the address translation logic is configured to enable translation of an external virtual address associated with a sector of the memory device to a physical address associated therewith.

16. The method of claim 15 , comprising providing an array of one of Read-Only Memory (ROM) cells and Flash memory cells as the array of non-volatile memory cells, and an array of Random Access Memory (RAM) cells as the array of volatile memory cells.

17. The method of claim 15 , further comprising enabling access to at least one of the array of non-volatile memory cells, the array of volatile memory cells and the hybrid memory through a memory controller associated with the memory device.

18. The method of claim 17 , wherein enabling access to the at least one of the array of non-volatile memory cells, the array of volatile memory cells and the hybrid memory through the memory controller includes at least one of: enabling a memory read operation from one of the array of non-volatile memory cells, the array of volatile memory cells and the hybrid memory; enabling an erase operation on one of the array of non-volatile memory cells and a non-volatile portion of the hybrid memory; enabling a memory write operation to the one of the array of non-volatile memory cells, the array of volatile memory cells and the hybrid memory; enabling a transfer operation signifying copying data from a volatile portion of the hybrid memory to a non-volatile portion therein; enabling a recall operation signifying one of copying data from the non-volatile portion of the hybrid memory to the volatile portion therein and copying data from a portion of the array of non-volatile memory cells not including any portion of the hybrid memory to another portion therein through a buffer associated therewith; enabling a register read operation through the memory device to allow reading of registers associated with the memory device, the registers including at least the set of registers associated with the address translation logic; and enabling a register write operation through the memory device to allow writing to the registers associated with the memory device through transmission of an operation code associated with an appropriate type of access of the memory device from the memory controller to the memory device, the appropriate type of access indicating the corresponding one of the memory read operation, the erase operation, the memory write operation, the transfer operation, the recall operation, the register read operation, and the register write operation.

19. The method of claim 18 , further comprising: driving an enable signal to an appropriate level through the memory controller to initiate the transmission of the operation code; and timing the corresponding one of the memory read operation, the erase operation, the memory write operation, the transfer operation, the recall operation, the register read operation, and the register write operation based on one of a rising edge and a falling edge of a clock associated with an interface configured to couple the memory device to the memory controller.

20. The method of claim 19 , wherein the erase operation includes one of an erase memory operation configured to erase all content associated with the one of the array of non-volatile memory cells and the non-volatile portion of the hybrid memory, an erase sector operation configured to erase all content associated with a sector of the one of the array of non-volatile memory cells and the non-volatile portion of the hybrid memory, and an erase page operation configured to erase all content associated with a page of the sector of the one of the array of non-volatile memory cells and the non-volatile portion of the hybrid memory.

21. The method of claim 19 , wherein at least one of the memory read operation, the erase operation, the memory write operation, the transfer operation and the recall operation includes: comparing a memory access address associated therewith an address associated with a corresponding sector of the one of the array of non-volatile memory cells, the array of volatile memory cells and the hybrid memory stored in an address map register associated with the address translation logic through a comparator associated with the address map register; and enabling an appropriate memory access to the corresponding one of the array of non-volatile memory cells, the array of volatile memory cells and the hybrid memory based on the comparison through the comparator associated with the address map register.

22. The method of claim 21 , further comprising sequentially performing the transfer operation between the volatile portion of the hybrid memory and the non-volatile portion therein one modified memory page at a time, wherein the modified memory page signifies a page associated with a corresponding sector of the hybrid memory including data that has been modified following a previous transfer operation associated therewith, wherein a tag bit associated with the modified memory page indicates the modified status thereof, and wherein the tag register includes the tag bit associated with the modified memory page.

23. The method of claim 21 , further comprising sequentially performing the recall operation between the one of the non-volatile portion of the hybrid memory and the volatile portion therein and the portion of the array of non-volatile memory cells not including any portion of the hybrid memory and the another portion therein one memory page at a time.