Apparatuses, Systems, Devices, and Methods of Replacing at Least Partially Non-Functional Portions of Memory

1. A method comprising: providing with an initial storage capacity; subsequently determining that a portion of the memory is at least partially non-functional; replacing the portion of at least partially non-functional memory with a portion of said memory previously allocated to error detection and/or correction, wherein replacing provides a total amount of functional memory having a storage capacity substantially equal to the initial storage capacity; and adjusting an error detection and/or correction process responsive to determining that the portion of the memory is at least partially non-functional and/or replacing the portion of at least partially non-functional memory.

2. The method of claim 1 , wherein said replacing the portion of at least partially non-functional memory includes: transferring signal or state information from the portion of at least partially non-functional memory; and adjusting a memory map.

3. The method of claim 1 , wherein determining that a portion of said memory is at least partially non-functional comprises determining the non-functional portion of said memory by detecting a difference between signal or state information read from said memory using error codes and signal or state information read from said memory without using error codes.

4. The method of claim 1 , wherein adjusting the error detection and/or correction process comprises using an error code with fewer bits for selected memory locations.

5. The method of claim 1 , wherein said memory comprises portions of memory arrays from multiple memory devices.

6. The method of claim 1 , wherein adjusting the error detection and/or correction process comprises reducing a size of error detection and/or correction codes.

7. The method of claim 1 , wherein said at least partially non-functional memory comprises non-functional memory.

8. The method of claim 1 , wherein determining that said portion of a memory is at least partially non-functional comprises comparing a number of errors associated with the portion to an error threshold.

9. A method comprising: providing with an initial storage capacity; subsequently adaptively reducing memory error detection and/or correction ability in response to identifying an error-prone memory location in a portion of the memory; and using an error code (EC) memory portion to store signal or state information previously stored in the identified memory location, wherein using provides a total amount of non error-prone memory locations having a storage capacity substantially equal to the initial storage capacity.

10. The method of claim 9 , wherein said identifying error-prone memory location comprises: for one or more memory locations, reading signal or state information from the memory locations with and without using error code detection and/or correction; and determining a difference in signal or state information read from a particular memory location using error code detection and/or correction and signal or state information read from the particular memory location without using error code detection and/or correction.

11. The method of claim 9 , wherein said memory comprises a solid state drive (SSD).

12. The method of claim 9 , further comprising determining whether a particular portion of said memory is at least partially non-functional based, at least in part, on identifying error-prone memory locations in the particular portion; and wherein using the EC memory portion comprises substituting the at least partially non-functional portion of said memory with said EC memory portion.

13. The method of claim 12 , further comprising: using said error correction and/or detection to detect and/or correct one or more memory errors.

14. A non-volatile memory device comprising: a memory with an initial storage capacity, said memory including one or more portions allocated to store error code (EC)-related signal or state information and one or more portions allocated to store non-EC signal or state information; and a controller to remap memory locations in the one or more non-EC portions that are determined to be error prone to memory locations in the one or more EC-related portions, wherein a remapping provides a total amount of non-EC portions having a storage capacity substantially equal to the initial storage capacity, and wherein said controller is able to adjust error correction and/or detection used with said memory.

15. The non-volatile memory device of claim 14 , wherein said non-volatile memory device comprises a solid state drive.

16. The non-volatile memory device of claim 14 , wherein said memory device is incorporated in at least one of the following: a desktop computer, a laptop computer, a workstation, a server device, a personal digital assistant, a mobile communication device, or any combination thereof.

17. A system comprising: memory with an initial storage capacity and including a first number of memory sectors to store error code (EC)-related signal or state information and a second number of memory sectors to store other signal or state information, said memory further including a memory controller to: access signal or state information stored in memory locations in said second number of memory sectors; identify one or more at least partially non-functional sectors of said second number of memory sectors; and use one or more sectors in said first number of memory sectors as a substitute for said one or more at least partially non-functional sectors, wherein a substitution provides a total amount of said second number of memory sectors having a storage capacity substantially equal to the initial storage capacity.

18. The system of claim 17 , wherein said memory controller is able to remap memory locations between sectors.

19. The system of claim 18 , wherein a remap of memory locations between sectors includes a transfer of stored signal or state information between memory locations.

20. The system of claim 17 , and further comprising a processor coupled to said memory.

21. The system of claim 20 , wherein said controller is further able to adaptively reduce the error detection and/or correction used with said memory.

22. The system of claim 17 , wherein said controller is further able to adaptively increase the number of states stored per cell in said first number of memory sectors to compensate for loss of memory capacity in said at least partially non-functional sectors.

23. The system of claim 21 , wherein said controller is further able to, in connection with identifying one or more at least partially non-functional sectors, read signal or state information from said memory using error codes and read signal or state information from said memory without using error codes.

24. An apparatus comprising: a plurality of integrated circuit (IC) memory chips with an initial storage capacity; and a memory controller to: determine that one or more memory sectors of said IC memory chips is at least partially non-functional; adjust error correction and/or detection for one or more sectors of said IC memory chips; and replace the one or more at least partially non-functional sectors with one or more sectors allocated to error detection and/or correction, where a replacing provides a total amount of functional memory having a storage capacity substantially equal to the initial storage capacity.

25. The apparatus of claim 24 , wherein, for a memory sector of said IC memory chips, said memory controller is able to determine a difference between signal or state information read from said memory sector using error correction and/or detection and signal or state information read without using error correction and/or detection.

26. The apparatus of claim 24 , wherein to adjust error detection and/or correction for one or more sectors, said controller is able to apply an error code with fewer bits for the one or more sectors.