Hybrid Mechanism for More Efficient Emulation and Method Therefor

1. In a host system, a method for using instruction scheduling to efficiently emulate the operation of a target computing system, said method comprising: (a) preparing, on the host system, an instruction sequence to interpret an instruction written for execution on the target computing system; (b) performing instruction scheduling on the instruction sequence, to achieve an efficient instruction level parallelism, for the host system; and (c) inserting, a separate and independent instruction sequence, which, when executed simultaneously with the instruction sequence produced by (b), performs the following: i) copies to a separate location a minimum instruction sequence necessary to execute an intent of an interpreted target instruction, said interpreted target instruction being a translation; and ii) modifies the interpreter code such that a next interpretation of said target instruction results in execution of the translated version, thereby removing execution of interpreter overhead.

2. The method of claim 1 , further comprising: (d) executing, on the host system, a result of performing (c) above.

3. The method of claim 1 , wherein the instruction scheduling of (b) is performed with respect to a very long instruction word (VLIW) architecture of said target computing system.

4. The method of claim 1 , wherein the interpretation is conducted with reference to a stream of bytecodes of the target computing system.

5. The method of claim 4 , wherein said bytecodes comprise Java® bytecodes.

6. A host system for using instruction scheduling to efficiently emulate the operation of a target computing system, said host system comprising a memory having tangibly embodied therein a set of instructions for: (a) an interpreter for preparing, on the host system, an instruction sequence to interpret an instruction written for execution on the target computing system; (b) a scheduler for performing instruction scheduling on the instruction sequence, to achieve an efficient instruction level parallelism as represented by pipeline delay slots, for the host system; and (c) a translator for inserting, in the pipeline delay slots, a separate and independent instruction sequence, which, when executed simultaneously with the instruction sequence produced by (b), performs the following: i) copies to a separate location a minimum instruction sequence necessary to execute an intent of an interpreted target instruction, said interpreted target instruction being a translation; and ii) modifies the interpreter code such that a next execution of said target instruction results in execution of the translated version, thereby removing execution of interpreter overhead.

7. A non-transitory storage medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus to perform a method of, in a host system, using instruction scheduling to efficiently emulate the operation of a target computing system, said method comprising: (a) preparing, on the host system, an instruction sequence to interpret an instruction written for execution on the target computing system; (b) performing instruction scheduling on the instruction sequence, to achieve an efficient instruction level parallelism, for the host system; and (c) inserting a separate and independent instruction sequence, which, when executed simultaneously with the instruction sequence produced by (b), performs the following: i) copies to a separate location a minimum instruction sequence necessary to execute an intent of an interpreted target instruction, said interpreted target instruction being a translation; and ii) modifies the interpreter code such that a next interpretation of said target instruction results in execution of the translated version, thereby removing execution of interpreter overhead.