Methods of Performing Error Detection/Correction in Nonvolatile Memory Devices

1. A method of operating a memory device, comprising: identifying at least one weak string as weak column information; and performing an error correction operation on a first plurality of bits of data read from a plurality of strings of non-volatile memory cells using an algorithm that modifies a weighting of the reliability of one or more data bits in the first plurality of bits of data based on the weak column information, wherein said performing comprises performing an error correction operation on the first plurality of bits of data read from the plurality of strings using an algorithm that interprets a bit of data read from the at least one weak string as having a relatively reduced reliability relative to other ones of the first plurality of data bits.

2. The method of claim 1 , further comprising testing the plurality of strings of nonvolatile memory cells in the memory device to identify at least one weak string therein having a higher probability of yielding erroneous read data error relative to other ones of the plurality of strings.

3. The method of claim 1 , further comprising storing the identity of the at least one weak string as weak column information.

4. The method of claim 1 , further comprising calculating a probability of error associated with each of the first plurality of bits of data.

5. The method of claim 1 , further comprising calculating a probability of error associated with each of the first plurality of bits of data by determining a log-likelihood ratio (LLR) for each of the first plurality of bits of data.

6. The method of claim 1 , wherein said performing comprises modifying a value of a bit of data read from the at least one weak string in advance of performing an error correction operation on the first plurality of bits of data.

7. A method for processing data read from a memory device, comprising: receiving weak column (WC) information of the memory device; calculating the probability of each of the bits of the data; modifying the probability of the bits, corresponding to the WC information, among the bits of the data; and performing an error correction operation on the basis of the modified probability, wherein in the calculating of the probability, the probability is a likelihood ratio (LR) or a log-likelihood ratio (LLR) for each of the bits of the data.

8. The method of claim 7 , wherein the WC information includes an address of a defective column or a column with back pattern dependency, among the columns of the nonvolatile memory device.

9. The method of claim 7 , wherein in the modifying of the probability of the bits corresponding to the WC information, the probability of the bits corresponding to the WC information is controlled to be smaller than the probability of normal bits.

10. The method of claim 7 , wherein a soft decision decoding operation is performed in the performing of the error correction operation.

11. A method for processing data read from a memory device, comprising: receiving weak column (WC) information of the memory device; setting the bit, corresponding to a weak column, among the bits of the data to an erasure with reference to the WC information; and performing an error correction operation on the data, including the bit set to the erasure, according to an erasure decoding scheme, wherein the performing of the error correction operation comprises: a first decoding operation of substituting a logic ‘0’ for an erasure bit of the data including the erasure and performing an error correction operation; and a second decoding operation of substituting a logic ‘1’ for the erasure bit of the data including the erasure and performing an error correction operation.

12. The method of claim 11 , wherein in the setting of the bit to erasure, the WC information is provided as location information of the erasure.

13. The method of claim 11 , further comprising selecting the output data of the operation, which is treated as a decoding success, among the first decoding operation and the second decoding operation, as the final read data.

14. The method of claim 11 , wherein the performing of the error correction operation further comprises: generating a plurality of candidate data by substituting a combination of a logic ‘0’ or a logic ‘1’ for the erasure bit of the data including the erasure; and performing the error correction operation on the candidate data.

15. The method of claim 14 , further comprising selecting the output data, treated as a decoding success, among the candidate data as the final read data.

16. The method of claim 14 , further comprising selecting one of the candidate data as the final output data if there are at least two candidate data treated as a decoding success by the error correction operation.

17. A memory system comprising: a memory device; and a memory controller determining each of the bits of read data, received from the memory device, according to a soft decision decoding scheme with reference to weak column (WC) information, wherein a weight different from a normal bit is applied to the bit, corresponding to the WC information, among the bits of the read data in the soft decision decoding scheme, wherein the memory controller comprises: a WC management unit setting a weak column of the read data with reference to the WC information; and a soft decision decoder determining each of the bits of the read data according to the maximum likelihood criterion with reference to the WC information.

18. The memory system of claim 17 , wherein the soft decision decoder comprises: a likelihood ratio (LR) calculation unit calculating a probability value of each of the bits of the read data; and an error correction decoder correcting the probability value with reference to the WC information and correcting an error in the read data with reference to the corrected probability value.

19. The memory system of claim 18 , wherein the soft decision decoder further comprises an a posteriori probability unit calculating an a posteriori probability of the bits of the read data, wherein the probability value includes a likelihood ratio (LR) or a log-likelihood ratio (LLR).

20. The memory system of claim 17 , wherein the WC information is stored and updated in a predetermined region of the nonvolatile memory device.

21. The memory system of claim 17 , wherein the WC information is stored and updated in a memory device of the memory controller.

22. The memory system of claim 17 , wherein the WC information is detected in a merge operation or a test process of the nonvolatile memory device and is stored in the nonvolatile memory device.

23. The memory system of claim 17 , wherein the nonvolatile memory device is a three-dimensional semiconductor memory device comprising vertical strings.