Spatial Light Modulator with Masking-Comparators

1. A device comprising: a spatial light modulator comprising a plurality of masking-processors, wherein the plurality of masking processors comprise parallel processing elements (PPE) for computing a respective drive waveform for each pixel of a plurality of pixels on the spatial light modulator, wherein each masking-processor comprises logic circuitry for logically and/or arithmetically comparing one or more multiple-bit pixel control values to one or more multiple-bit match values, wherein the PPE are part of execution RAM (ERAM) and PPE processing (EPE) modules located on at least three sides of a mirror RAM (MRRAM) array of the spatial light modulator, and wherein each EPE module comprises ERAM for the PPE of the EPE module.

2. The device of claim 1 , wherein each masking-processor masks one or more bit positions when comparing one or more multiple-bit pixel control values to one or more multiple-bit match values for each pixel of the plurality of pixels.

3. The device of claim 1 , wherein the device comprises a masking-loader for writing to storage one or more multiple-bit pixel control values when masked by each masking-processor.

4. The device of claim 1 , wherein the masking-processor comprises one or more masking comparators.

5. The device of claim 1 , wherein the EPE modules are located on four sides of the MRRAM array.

6. A device comprising: a spatial light modulator comprising parallel processing elements (PPE) for computing a respective drive waveform for each respective pixel of a plurality of pixels on the spatial light modulator, and a command sequencer for generating a sequence of one or more programmable match values, wherein each parallel processing element of the parallel processing elements comprises logic circuitry for logically and/or arithmetically comparing one or more multiple-bit pixel control values for a respective pixel of the plurality of pixels to the one or more programmable match values for the respective pixel, and wherein the PPE are part of execution RAM (ERAM) and PPE processing (EPE) modules located on at least three sides of a mirror RAM (MRRAM) array of the spatial light modulator, and wherein each EPE module comprises ERAM for the PPE of the EPE module.

7. The device of claim 6 , wherein each parallel processing element comprises masking-logic for ignoring one or more bits of the one or more multiple-bit pixel control values and/or the programmable match values when comparing the one or more multiple-bit pixel control values to the one or more programmable match values.

8. The device of claim 6 , wherein the command sequencer generates the sequence of one or more multiple-bit match values based on one or more multiple-bit match values fetched from one or more memories of the device.

9. The device of claim 6 , wherein the command sequencer comprises a function generator for generating the sequence of one or more multiple-bit match values.

10. The device of claim 6 , wherein each parallel processing element comprises one or more masking comparators.

11. The device of claim 6 , wherein the EPE modules are located on four sides of the MRRAM array.

12. A device comprising: a spatial light modulator comprising: parallel processing elements (PPE), a pixel control value storage, and a mirror RAM (MRRAM) array, wherein the PPE are part of execution RAM (ERAM) and PPE processing (EPE) modules located on at least three sides of the MRRAM array of the spatial light modulator, and wherein each EPE module comprises ERAM for the PPE of the EPE module.

13. The device of claim 12 , wherein the ERAM-aligned architecture comprises a butterflied-ERAM-and-processors architecture.

14. The device of claim 12 , wherein the EPE modules are located on four sides of the MRRAM array.

15. A method comprising the following steps: (a) controlling a pixel of a spatial light modulator based on a first multiple-bit pixel control value, (b) ignoring one or more first bits of the first multiple-bit pixel control value to thereby form one or more ignored bits, and (c) storing one or more second bits for a second multiple-bit pixel control value in respective storage locations of the one or more ignored bits, wherein the pixel of the spatial light modulator is controlled based on the second multiple-bit pixel control value, wherein steps (a) and (b) are conducted by parallel processing elements (PPE) of the spatial light modulator, and wherein the PPE are part of execution RAM (ERAM) and PPE processing (EPE) modules located on at least three sides of an mirror RAM (MRRAM) array of the spatial light modulator, and wherein each EPE module comprises ERAM for the PPE of the EPE module.

16. The method of claim 15 , wherein the one or more first bits are used to control a first color of the pixel and wherein the one or more second bits are used to control a second color of the pixel.

17. The method of claim 15 , comprising the following step: (d) storing the first multiple bit pixel control value on the spatial light modulator prior to step (a).

18. The device of claim 15 , wherein the EPE modules are located on four sides of the MRRAM array.