Advanced multi line addressing

1. A circuit, realizing a flat panel display capable to display images, comprising: an image storage and processing block for storing and processing said images to be displayed; a display and timing controller block controlling said display operation; an image pixel matrix containing a multitude of row- and column- line arranged pixel elements; one or more controlled row driver blocks; one or more controlled column driver blocks; and a pixel display operation for displaying said pixel elements employing an advanced multi-line addressing operation applied to a row and/or column drive activated pixel element display operation, whereby said advanced multi-line addressing operation comprises during every operating sequence lossless decomposition of image pixel data by analyzing image pixel data from multiple lines for common contents by image pixel data comparison using only pixel data calculation algorithms for said lossless decomposition operation of image pixel data which are requiring only one single pass through said image pixel data within one image frame period, thereby separating common parts of said image pixel data into a multi-line data domain and residual parts of the image pixel data into a single line data domain thus allowing for a display of these two data domains in separately activated pixel element display operations, wherein the lossless decomposition is performed by maximizing multi-line data in the multi-line data domain and minimizing single-line data in the single-line data domain within one image frame period.

2. The circuit according to claim 1 wherein said pixel display operation for displaying said pixel elements is a sequentially operating pixel display operation for displaying said pixel elements employing an advanced multi-line addressing operation applied to a row and/or column drive activated sequential pixel element display operation.

3. The circuit according to claim 1 whereby said advanced multi-line addressing operation signifies that during every operating sequence a decomposition operation of said image pixel data is taking place by analyzing image pixel data from multiple lines for common contents by simple pixel data comparison, separating the common parts of said image pixel data into a multi-line data domain and the residual parts of the image pixel data into a single line data domain thus allowing for a separate display of the two data domains immediately following each other in separately activated sequential pixel element display operations.

4. The circuit according to claim 1 whereby said advanced multi-line addressing operation signifies that during every operating sequence a decomposition operation of said image pixel data is taking place by analyzing said image pixel data from multiple lines for common contents by simple pixel data comparison, separating the common parts of said image pixel data into a multi-line data domain and the residual parts of said image pixel data into a single line data domain thus allowing for an interleaved display of the two data domains each with separately activated sequential pixel element display operations.

5. The circuit according to claim 1 wherein said image pixel matrix comprises a passive matrix device.

6. The circuit according to claim 1 wherein said image pixel matrix comprises an active matrix device.

7. The circuit according to claim 1 wherein said image storage and/or processing block comprises memory for more than one image frame.

8. The circuit according to claim 1 wherein said image storage and/or processing block comprises memory for only one single image frame.

9. The circuit according to claim 1 wherein said image storage and/or processing block comprises memory for a partial image frame only.

10. The circuit according to claim 1 wherein said image storage and/or processing block comprises a digital processor.

11. The circuit according to claim 10 wherein said digital processor comprises an ASIC device.

12. The circuit according to claim 10 wherein said digital processor comprises an FPGA device.

13. The circuit according to claim 10 wherein said digital processor comprises a general purpose CPU and memory.

14. The circuit according to claim 13 wherein said memory comprises RAM.

15. The circuit according to claim 13 wherein said memory comprises ROM.

16. The circuit according to claim 1 wherein the components of said blocks are MOSFET components.

17. The circuit according to claim 16 wherein said MOSFET components are of the CMOS type.

18. The circuit according to claim 1 wherein said pixel elements comprise LEDs.

19. The circuit according to claim 18 wherein said LEDs comprise OLEDs.

20. The circuit according to claim 18 wherein said LEDs comprise PLEDs.

21. A circuit, realizing a flat panel display capable to display images, comprising: an image storage and processing means; a display and timing controller means; an image displaying means containing a multitude of row- and column- line arranged pixel elements; one or more row controlling means; one or more column controlling means; and a pixel display operation for displaying said pixel elements employing an advanced multi-line addressing operation applied to a row and/or column drive activated pixel element display operation, whereby said advanced multi-line addressing operation comprises during every operating sequence lossless decomposition of image pixel data by analyzing image pixel data from multiple lines for common contents by image pixel data comparison using only image pixel data calculation algorithms for said lossless decomposition operation of image pixel data which are requiring only one single pass through said image pixel data within one image frame period, thereby separating common parts of said image pixel data into a multi-line data domain and residual parts of said image pixel data into a single line data domain thus allowing for a display of the two data domains in separately activated pixel element display operations, wherein the lossless decomposition is performed by maximizing multi-line data in the multi-line data domain and minimizing single-line data in the single-line data domain within one image frame period.

22. The circuit according to claim 21 wherein said pixel display operation for displaying said pixel elements is a sequentially operating pixel display operation for displaying said pixel elements employing an advanced multi-line addressing operation applied to a row and/or column drive activated sequential pixel element display operation.

23. The circuit according to claim 21 whereby said advanced multi-line addressing operation signifies that during every operating sequence a decomposition operation of said image pixel data is taking place by analyzing said image pixel data from multiple lines for common contents by simple pixel data comparison, separating the common parts of said image pixel data into a multi-line data domain and the residual parts of said image pixel data into a single line data domain thus allowing for a separate display of the two data domains immediately following each other in separately activated sequential pixel element display operations.

24. The circuit according to claim 21 whereby said advanced multi-line addressing operation signifies that during every operating sequence a decomposition operation of said image pixel data is taking place by analyzing said image pixel data from multiple lines for common contents by simple pixel data comparison, separating the common parts of said image pixel data into a multi-line data domain and the residual parts of said image pixel data into a single line data domain thus allowing for an interleaved display of the two data domains each with separately activated sequential pixel element display operations.

25. A method for implementing a power saving advanced multi-line addressing algorithm for panel display drivers, comprising: providing a flat panel display device with a plurality of selectively activatable pixel elements arranged in an array of orthogonally oriented rows and columns capable to display image data frames; providing according image data storage and processing means as well as display and timing controlling means; providing according row and column driver circuits for the selectively activatable pixel elements; fetching at least two lines of an original image data frame from the image data storage and processing means for appropriate advanced multi-line addressing algorithm operations employing more than one line of the image data; decomposing losslessly the fetched lines of image data into multi-line domain and single line domain data in such a way, that multiple lines are compared pairwise to each other in order to find their common contents which then is outputted as image data into related lines of the multiple line domain, these lines being commonly identical to all the currently compared lines thus forming a group of lines all with identical image data whereas the left over residual data of each compared pair of the multiple lines currently compared are singled out into accordingly related single lines in the single line domain data with singly individual image data; whereby these comparing prescriptions above define the core of the advanced multi-line addressing algorithm using only image pixel data calculation algorithms for said decomposition operation of image pixel data which are requiring only one single pass through said image pixel data within one image frame period, wherein the lossless decomposition is performed by maximizing multi-line data in the multi-line data domain and minimizing single-line data in the single-line data domain within one image frame period; preparing the data from the multi-line domain and the data from the single line domain in such a way that two frames of image data are saved into distinct multi-line and single line domain frames according to the output of the decomposition in step ‘decomposing’ above by looping back to step ‘fetching’ above until all image data lines of the original image data frame are processed according to the advanced multi-line addressing algorithm; scanning sequentially the selectable display pixel elements of the array by selecting groupwise all the rows from the multi-line domain frame groups with identical common contents thus activating all row/scan drivers for the accordingly selected rows from each currently selected group of the frame; driving for all selected rows of a certain active group with identical common contents from the multi-line domain frame all the selected display pixel elements for every column sequentially or at the same time whilst activated by the current scan operation with the identical image data from the currently active group in the multi-line domain thus activating collectively all column/data drivers for the accordingly selected columns from each active group; scanning sequentially the selectable display pixel elements of the array by selecting every single line with singly individual image data from the single line domain frame thus sequentially activating row by row all the row/scan drivers for each row of the frame; driving for all selected active rows with singly individual image data from the single line domain frame all the selected display pixel elements for every column sequentially or at the same time whilst activated by the current scan operation with the singly individual image data from the single line domain thus activating collectively all column/data drivers for the accordingly selected columns for each active row; and repeating all the ‘scanning’ and ‘driving’ steps above continuously until all group of lines all with identical image data from the multi-line domain and all singly individual image data from the single line domain are being operated upon whereby its order is arbitrary.

26. The method according to claim 25 wherein said step of decomposing comprises a decision operation accounting for special cases or policies where the drive time for the multi-line driving from the M domain and the single line driving from the S domain for two rows sums up to a value greater than the drive time for two single lines in conventional linear scan mode.

27. The method according to claim 25 whereby said steps of driving all the selected display pixel elements for every column are completed until all image data of either domain are displayed.

28. The method according to claim 25 whereby said steps of driving all the selected display pixel elements for every column are realized in such a way, that image data from either domain are appropriately interleaved and displayed.

29. A method for implementing an advanced multi-line addressing algorithm for flat panel displays comprising: providing an image displaying means containing a multitude of in pixel rows and pixel columns arranged pixel elements capable of displaying image data in form of image data frames; providing an image storage and processing means capable to implement uniquely advanced multi-line addressing algorithm related parts regarding storing and processing calculations of the image data frames; providing a display and timing controller means capable to implement uniquely advanced multi-line addressing algorithm related parts regarding synchronous and sequential control and drive operations on the image data frames; providing one or more pixel row controlling means capable to scan display pixels according to the uniquely advanced multi-line addressing algorithm related prescriptions; providing one or more pixel column controlling means capable to drive display pixels according to the uniquely advanced multi-line addressing algorithm related prescriptions; establishing as advanced multi-line addressing algorithm a sequentially operating multi-line addressing mechanism for addressing and driving the pixel elements by the pixel row and column controlling means in such a way that a lossless decomposition of the image data into multi-line domain and single line domain data takes place using only image pixel data calculation algorithms for said lossless decomposition operation of image pixel data which are requiring only one single pass through said image pixel data, whereby multiple lines of image data frames are compared pairwise to each other in order to find their common contents, wherein the lossless decomposition is performed by maximizing multi-line data in the multi-line data domain and minimizing single-line data in the single-line data domain within one image frame period; determining as first part of the advanced multi-line addressing algorithm the common contents of multiple image data lines by comparing pixelwise two lines of image data whereby the common contents from each compared pair of pixels is then outputted as identical image data from both of these compared lines into the related pixels in the related lines of the multiple line domain; identifying as second part of the advanced multi-line addressing algorithm the left over residual data of each currently compared pair of the multiple image data lines as individual contents singled out into accordingly related single lines of the single line domain with singly individual image data in such a way that if both image data of the compared pixels in the currently compared lines are identical the resulting single line image data for the related pixels are both zero, if the image data of the compared pixels are different one single line image datum contains that positive difference whereas the other contains zero as image data in the related pixels of the related single lines of the single line domain; continuing as third part of the advanced multi-line addressing algorithm the comparing and identifying for the next pair of lines of image data by looping back to step ‘determining’ above until all lines of the currently processed image data frame are being operated upon, thus creating groups of lines each with identical image data in the multi-line domain if lines are identical to all the lines compared before and accordingly generating the related single lines with individual image data in the single line domain; operating the row driver circuits as multiplexed scan drivers capable to select one or more rows of display pixels and operate the column driver circuits as image data drivers capable to drive one or more columns of display pixels for one or more rows, both sequentially or at the same time according to the prescriptions of the advanced multi-line addressing algorithm; displaying groups of common image data from the multi-line domain in a groupwise synchronously pixel element data display operation for every pixel element in each column during the pixel driving activations for the current frame; and displaying individual image data in the single line domain in a pixel element data display operation for pixel elements in each column during the pixel driving activations for the current frame.

30. The method according to claim 29 wherein said step of groups of common image data from the multi-line domain is a step of displaying sequentially all the groups of common image data from the multi-line domain in a groupwise synchronously pixel element data display operation for every pixel element in each column during an all the multiple rows of the group comprising sequence of pixel driving activations for the current frame.

31. The method according to claim 29 wherein said step of displaying individual image data in the single line domain is a step of displaying sequentially the individual image data from every line in the single line domain in a pixel element data display operation for every pixel element in each column during the single row oriented sequence of pixel activations for the current frame.

32. The method according to claim 29 wherein said two steps of displaying groups of common image data from the multi-line domain and of displaying individual image data in the single line domain are combined into one step where the operations of each original step are being interleaved appropriately.

33. A method for implementing a power saving advanced multi-line addressing algorithm for panel display drivers, comprising: providing a flat panel display device with row and column driver circuits comprising according image data storage and processing means as well as display and timing controlling means; decomposing losslessly lines of image data into multi-line domain and single line domain data in such a way, that multiple lines are compared pairwise to each other in order to find their common contents which then is outputted as image data into related lines of the multiple line domain, these lines being commonly identical to all the currently compared lines thus forming a group of lines all with identical image data whereas the left over residual data of each compared pair of the multiple lines currently compared are singled out into accordingly related single lines in the single line domain data with singly individual image data; whereby these comparing prescriptions above define the core of the advanced multi-line addressing algorithm using only image pixel data calculation algorithms for said decomposition operation of image pixel data which are requiring only one single pass through said image pixel data, wherein the lossless decomposition is performed by maximizing multi-line data in the multi-line data domain and minimizing single-line data in the single-line data domain within one image frame period.

34. A method for implementing an advanced multi-line addressing algorithm for flat panel displays comprising: providing image displaying means with pixel and column row controlling means and image storage and processing means as well as display and timing controller means; establishing as advanced multi-line addressing algorithm a sequentially. operating multi-line addressing mechanism for addressing and driving the pixel elements by the pixel row and column controlling means in such a way that a lossless decomposition of the image pixel data into multi-line domain and single line domain data is accomplished using only image pixel data calculation algorithms for said decomposition operation of image pixel data which are requiring only one single pass through said image pixel data, whereby multiple lines of image data are compared pairwise to each other in order to find their common contents which is then allotted to multi-line domain data whereas the residual contents collates into single line domain data, wherein the lossless decomposition is performed by maximizing multi-line data in the multi-line data domain and minimizing single-line data in the single-line data domain within one image frame period.