8611263

Methods and Apparatus for Saving Power by Designating Frame Interlaces in Communication Systems

PublishedDecember 17, 2013
Assigneenot available in USPTO data we have
InventorsRajat Prakash
Technical Abstract

Patent Claims
32 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method for changing from a first number of frame interlaces to a second number of frame interlaces, the method comprising: receiving a request to change frame interlaces, the request including a supportable number of frame interlaces; identifying the second number of frame interlaces based on the supportable number of frame interlaces; and transmitting the identified second number of frame interlaces to an access terminal, the second number of frame interlaces identifying those frame interlaces that the access terminal is required to monitor.

2

2. The method of claim 1 , wherein the second number is smaller than the first number, when the available power at the access terminal has decreased.

3

3. The method of claim 1 , wherein the second number is larger than the first number, when the available power at the access terminal has increased.

4

4. The method of claim 1 , wherein said identifying comprises not assigning of the same frame interlace to two or more access terminals (ATs).

5

5. The method of claim 1 , wherein said identifying comprises aligning one of the identified frame interlaces on frames that carry power control channel.

6

6. The method of claim 5 , wherein said identifying comprises aligning a second one of the identified frame interlaces on frames adjacent to frames that carry power control channel.

7

7. The method of claim 1 , wherein said identifying comprises identifying the frame interlaces based on a request from an AT.

8

8. The method of claim 1 , further comprising receiving an acknowledgement message generated by the AT in response to transmitting said second number of frame interlaces.

9

9. The method of claim 1 , wherein the supportable number of frame interlaces is based on the available power at the access terminal.

10

10. A non-transitory computer-readable medium embodying program code for implementing a method for changing from a first number of frame interlaces to a second number of frame interlaces, the method comprising: receiving a request to change frame interlaces, the request including a supportable number of frame interlaces; identifying the second number of frame interlaces based on the supportable number of frame interlaces; and transmitting the identified second number of frame interlaces to an access terminal, the second number of frame interlaces identifying those frame interlaces that the access terminal is required to monitor.

11

11. The non-transitory computer readable medium of claim 10 , wherein said identifying comprises not assigning the same frame interlace to two or more access terminals (ATs).

12

12. The non-transitory computer readable medium of claim 10 , wherein said identifying comprises aligning one of the identified frame interlaces on frames that carry power control channel.

13

13. The non-transitory computer readable medium of claim 12 , wherein said identifying comprises aligning a second one of the identified frame interlaces on frames adjacent to frames that carry power control channel.

14

14. The non-transitory computer readable medium of claim 10 , wherein said identifying comprises identifying the frame interlaces based on a request from an AT.

15

15. The non-transitory computer readable medium of claim 10 , further comprising receiving an acknowledgement message generated by the AT in response to transmitting said second number of frame interlaces.

16

16. The non-transitory computer readable medium of claim 10 , wherein the supportable number of frame interlaces is based on the available power at the access terminal.

17

17. An apparatus for changing from a first number of frame interlaces to a second number of frame interlaces, comprising: means for receiving a request to change frame interlaces, including a supportable number of frame interlaces; means for identifying the second number of frame interlaces based on the supportable number of frame interlaces; and means for transmitting the identified second number of frame interlaces to an access terminal, the second number of frame interlaces identifying those frame interlaces that the access terminal is required to monitor.

18

18. The apparatus of claim 17 , wherein said identifying comprises means for not assigning of the same frame interlace to two or more access terminals (ATs).

19

19. The apparatus of claim 17 , wherein said identifying comprises means for aligning one of the identified frame interlaces on frames that carry power control channel.

20

20. The apparatus of claim 19 , wherein said identifying comprises means for aligning a second one of the identified frame interlaces on frames adjacent to frames that carry power control channel.

21

21. The apparatus of claim 17 , wherein said identifying comprises means for identifying the frame interlaces based on a request from an AT.

22

22. The apparatus of claim 17 , further comprising means for receiving an acknowledgement message generated by the AT in response to transmitting said second number of frame interlaces.

23

23. The apparatus of claim 17 , wherein the supportable number of frame interlaces is based on the available power at the access terminal.

24

24. At least one processor configured for changing from a first number of frame interlaces to a second number, the processor comprising: a first module that receives a request to change frame interlaces, the request including a supportable number of frame interlaces; a second module that identifies the second number of frame interlaces based on the supportable number of frame interlaces; and a third module that transmits the identified second number of frame interlaces to an access terminal, the second number of frame interlaces, identifying those frame interlaces that the access terminal is required to monitor.

25

25. The processor of claim 24 , wherein the second number is smaller than the first number, when the available power at the access terminal has decreased.

26

26. The processor of claim 24 , wherein the second number is larger than the first number, when the available power at the access terminal has increased.

27

27. The processor of claim 24 , wherein said second module does not assign the same frame interlace to two or more access terminals (ATs).

28

28. The processor of claim 24 , wherein said second module aligns one of the identified frame interlaces on frames that carry power control channel.

29

29. The processor of claim 28 , wherein said second module aligns a second one of the identified frame interlaces on frames adjacent to frames that carry power control channel.

30

30. The processor of claim 24 , wherein said second module identifies the frame interlaces based on a request from an AT.

31

31. The processor of claim 24 , further comprising receiving an acknowledgement message generated by the AT in response to transmitting said second number of frame interlaces.

32

32. The processor of claim 24 , wherein the supportable number of frame interlaces is based on the available power at the access terminal.

Patent Metadata

Filing Date

Unknown

Publication Date

December 17, 2013

Inventors

Rajat Prakash

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Cite as: Patentable. “METHODS AND APPARATUS FOR SAVING POWER BY DESIGNATING FRAME INTERLACES IN COMMUNICATION SYSTEMS” (8611263). https://patentable.app/patents/8611263

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METHODS AND APPARATUS FOR SAVING POWER BY DESIGNATING FRAME INTERLACES IN COMMUNICATION SYSTEMS — Rajat Prakash | Patentable