Packet Processor Verification Methods and Systems

1. A packet-processing device, comprising: a plurality of ports having a receive media access controller (RX MAC) and a transmit media access controller (TX MAC), wherein the TX MAC of a first port is selectably configurable to loop back packets to a RX MAC of the first port during a self-testing operation of the packet processing device; and a switching engine coupled to the plurality of ports, the switching engine being configured to: provide a test packet received from a packet generator to the TX MAC of the first port, and forward to the TX MAC of one or more second ports at least the test packet received from the RX MAC of the first port, or a copy of the received test packet, after the received test packet or its copy has been looped-back one or more times between the TX MAC of the first port and the RX MAC of the first port.

2. The packet processing apparatus of claim 1 , wherein the switching engine further includes: packet mirroring circuitry configured to make a copy of the looped-back test packet received from the RX MAC of the first port, then route the copied test packet to the TX MAC of the first port.

3. The processing apparatus of claim 2 , wherein the switching engine is configured to receive newly generated packets from the packet generator while looping-back previously received packets, or copies of the previously received packets, so that a volume of packets processed at the first port exceeds a volume of newly generated packets received from the packet generator.

4. The processing apparatus of claim 1 , wherein at least two ports among the plurality of ports include a TX MAC that is selectably configurable to loop back packets to its respective RX MAC during a self-testing operation of the packet processor while continuing to receive test packets from the packet generator.

5. The processing apparatus of claim 1 , wherein the switching engine circuit further includes analysis circuitry configured to detect packet processing errors caused by the plurality of ports during a self-test operation.

6. The processing apparatus of claim 5 , wherein the apparatus further comprises a management central processing unit (CPU) that configures the switching engine circuit based on commands from an external computer.

7. The processing apparatus of claim 6 , wherein the management CPU provides patterns for one or more test packets to be used for self-testing.

8. A method for testing a packet-processor that includes a plurality of ports having a receive media access controller (RX MAC) and a transmit media access controller (TX MAC), the method comprising: sending a test packet to the TX MAC of a first port; looping-back the test packet from the TX MAC of the first port to an RX MAC of the first port; receiving the looped-back test packet from the RX MAC of the first port; and routing the received looped-back test packet to a TX MAC of one or more other ports of the packet-processor.

9. The method of claim 8 , further comprising replicating the received looped-back test packet received from the RX MAC of the first port, then routing at least one of the received looped back test packet and the replicated test packet to the TX MAC of the first port to increase a volume of packets and to route a plurality of like test packets to the TX MAC of one or more second ports.

10. The method of claim 9 , wherein replicating the received looped-back test packet comprises replicating the packet at a packet mirror circuit of the packet processor.

11. The method of claim 9 , wherein looping-back the test packet from the TX MAC of the first port to the RX MAC of the first port occurs at the MAC level.

12. The method of claim 9 , further comprising detecting one or more packet processing errors that occur during packet transfer by at least one of the plurality of ports during self-testing.

13. The method of claim 12 , further comprising providing test patterns for the test packets based on one or more commands received from an external computer.

14. A chipset for implementing a packet-processing apparatus configured to perform self-testing, comprising: one or more integrated circuits that include: a plurality of ports having a receive media access controller (RX MAC) and a transmit media access controller (TX MAC), wherein the TX MAC of a first port is selectably configurable to loop back packets to a RX MAC of the first port during a self-testing operation of the packet processor; and a switching engine coupled to the plurality of ports, the switching engine being configured to: provide a test packet received from a packet generator to the TX MAC of the first port, and forward to the TX MAC of one or more second ports at least the test packet received from the RX MAC of the first port, or a copy of the received test packet, after the received test packet or its copy has been looped-back one or more times between the TX MAC of the first port and the RX MAC of the first port.

15. The chipset of claim 14 , wherein the switching engine circuit further includes: second circuitry so as to enable the switching engine circuit to replicate the looped-back test packet received from the RX MAC of the first port, then route the replicated test packet to the TX MAC of the first port.

16. The chipset of claim 15 , wherein the first circuitry and the second circuitry enable the switching engine circuit and the first port to create a storming operation to allow a plurality of like test packets routed to the TX MAC of one or more second ports.

17. The chipset of claim 16 , wherein each TX MAC is configurable during self-testing to loop back packets to its respective RX MAC.

18. The chipset of claim 14 , wherein the switching engine circuit further includes analysis circuitry configured to detect packet processing errors that occur during self-testing.

19. The chipset of claim 14 , further comprising pattern generating circuitry that provides patterns for one or more test packets to be used for self-testing.

20. A method for testing a packet-processor that includes a plurality of ports having a receive media access controller (RX MAC) and a transmit media access controller (TX MAC), the method comprising: sending a test packet to the TX MAC of a first port; looping-back the test packet from the TX MAC of the first port to an RX MAC; receiving the looped-back test packet from the RX MAC; and replicating the received looped-back test packet received from the RX MAC, then routing at least one of the received looped-back test packet and the replicated test packet to the TX MAC of the first port to increase a volume of packets and to route a plurality of like test packets to the TX MAC of one or more other ports of the packet-processor.