Apparatus and Method for Supporting Circuit Design, and Semiconductor Integrated Circuit

1. A circuit design support apparatus comprising: a selection unit to select a delay circuit from among two or more delay circuits with different wire load values, on the basis of a difference value in a physical parameter between a first path and a second path; and an arrangement unit to arrange the selected delay circuit on the first path or the second path, wherein: the first path is a path that leads to a clock signal input terminal of a first resister from a reference position of a clock signal line; and the second path includes a path leading to a clock signal input terminal of a second resister from the reference position of the clock signal line, and a path leading to a data signal input terminal of the first register from a data signal output terminal of the second register.

2. The circuit design support apparatus according to claim 1 , wherein the selection unit selects the delay circuit further on the basis of a delay time of a data signal supplied to the data signal input terminal with respect to a clock signal.

3. The circuit design support apparatus according to claim 1 , further comprising a storage unit to store a table in which values concerning at least one of a wiring length, a wiring resistance, a wiring capacitance and wiring delay and information identifying the delay circuit are stored in association with each other, wherein the selection unit selects the delay circuit on the basis of the table.

4. The circuit design support apparatus according to claim 1 , wherein by referring to a storage unit in which two or more inverter circuits and two or more wires having the different values concerning a wiring length, a wiring resistance, a wiring capacitance or wiring delay for connecting between the inverter circuits are stored, the arrangement unit creates the delay circuit in which an inverter circuit and a wire are combined and arranged.

5. The circuit design support apparatus according to claim 4 , wherein the wire extends over two or more layers.

6. The circuit design support apparatus according to claim 1 , wherein the physical parameter is one of a wiring length, a wiring resistance, a wiring capacitance and wiring delay.

7. A circuit design support method comprising: selecting, by a processor, a delay circuit from among two or more delay circuits with different wire load values, on the basis of a difference value in a physical parameter between a first path and a second path; and arranging, by the processor, the selected delay circuit on the first path or the second path, wherein: the first path is a path that leads to a clock signal input terminal of a first resister from a reference position of a clock signal line; and the second path includes a path leading to a clock signal input terminal of a second resister from the reference position of the clock signal line, and a path leading to a data signal input terminal of the first register from a data signal output terminal of the second register.

8. The circuit design support method according to claim 7 , wherein the physical parameter is one of a wiring length, a wiring resistance, a wiring capacitance and wiring delay.

9. A semiconductor integrated circuit comprising: a first register; a second register; and a delay circuit which has wire load that compensates for a difference value in a physical parameter between a first path and a second path, wherein: the first path is a path that leads to a clock signal input terminal of the first resister from a reference position of a clock signal line; and the second path includes a path leading to a clock signal input terminal of the second resister from the reference position of the clock signal line, and a path leading to a data signal input terminal of the first register from a data signal output terminal of the second register.

10. The semiconductor integrated circuit according to claim 9 , wherein the physical parameter is one of a wiring length, a wiring resistance, a wiring capacitance and wiring delay.

11. The semiconductor integrated circuit according to claim 9 , wherein the delay circuit is inserted in a data signal line connected to the data signal input terminal.