Verifying state integrity in state retention circuits

1. Apparatus for processing data comprising: data processing circuitry configured to perform data processing operations; a plurality of state retention circuits forming part of said data processing circuitry, said plurality of state retention circuits configured to hold respective state values at respective nodes of said data processing circuitry when said data processing circuitry enters a low power mode; a scan path connecting said plurality of state retention circuits together in series, such that when said data processing circuitry is in a scan mode said state values may be scanned into and out of said respective nodes; and a plurality of parity information generation elements coupled to said scan path and configured to generate parity information indicative of said respective state values held at said respective nodes by said state retention circuits, wherein said plurality of parity information generation elements are arranged to provide a parity path, such that an output parity value generated at an output of said parity path will invert if one of said respective state values changes, wherein said plurality of parity information generation elements are provided with a parity element voltage supply which is configured to keep said parity information generation elements active with a full or reduced supply voltage when said data processing circuitry enters said low power mode and when said data processing circuitry is in said scan mode, and wherein said parity element voltage supply is configured to reduce or switch off the power supplied to said parity information generation elements when said data processing circuitry performs data processing operations not in said scan mode.

2. Apparatus as claimed in claim 1 , wherein said state retention circuits comprise a plurality of scan flops.

3. Apparatus as claimed in claim 1 , wherein said plurality of parity information generation elements are coupled to said scan path at respective scan path outputs of said state retention circuits.

4. Apparatus as claimed in claim 1 , wherein said scan path comprises hold time fixing buffers on said scan path at respective scan path outputs of said state retention circuits, and said plurality of parity information generation elements are coupled to respective outputs of said hold time fixing buffers.

5. Apparatus as claimed in claim 1 , wherein said parity information generation elements are arranged to provide said parity path by an output of a first parity information generation element forming one input of a next parity information generation element.

6. Apparatus as claimed in claim 1 , wherein said parity information generation elements are 2-input devices.

7. Apparatus as claimed in claim 1 , wherein said parity information generation elements have more than two inputs.

8. Apparatus as claimed in claim 1 , wherein said parity information generation elements are XOR gates.

9. Apparatus as claimed in claim 1 , wherein said parity information generation elements have multiple outputs.

10. Apparatus as claimed in claim 1 , wherein said plurality of state retention circuits each comprises a scan-in input and a dedicated scan-out output, said dedicated scan-out output of a first state retention circuit being connected to said scan-in input of a next state retention circuit to provide said scan path, wherein said scan path provides said parity path.

11. Apparatus as claimed in claim 10 , wherein said plurality of parity information generation elements are provided within said plurality of state retention circuits.

12. Apparatus as claimed in claim 11 , wherein said plurality of state retention circuits are configured to be responsive to assertion of a scan enable signal to enter a scan mode in which said state values may be scanned into and out of said respective nodes, and said plurality of parity information generation elements are configured to be responsive to said scan enable signal, such that when said scan enable signal is not asserted said parity information generation elements cause values at said dedicated scan-out outputs to depend on values at said scan-in inputs and said respective state values held at said respective nodes by said state retention circuits.

13. Apparatus as claimed in claim 1 , comprising at least one further state retention circuit coupled to said data processing circuitry, for which said plurality of parity information generation elements do not generate parity information indicative of at least one further state value held by said at least one further state retention circuit.

14. Apparatus as claimed in claim 1 , wherein said low power mode is a halt mode.

15. Apparatus as claimed in claim 1 , wherein said low power mode is a reduced voltage mode.

16. Apparatus as claimed in claim 1 , wherein said plurality of state retention circuits is provided with a retention voltage supply, said retention voltage supply being configured to provide a sufficient voltage to said plurality of state retention circuits to hold said respective state values at said respective nodes of said data processing circuitry when said data processing circuitry enters said low power mode, wherein said plurality of parity information generation elements are powered by said retention voltage supply.

17. Apparatus as claimed in claim 1 , wherein said parity element voltage supply is configured to be reduced when said state values are scanned into and out of said respective nodes via said scan path.

18. Apparatus as claimed in claim 1 , wherein said plurality of parity information generation elements are configured to be power-gated off when said data processing circuitry is not in said low power mode.

19. Apparatus as claimed in claim 1 , wherein at least one of said plurality of state retention circuits is configured to be responsive to a retention signal to enter a state retention mode, and at least one of said plurality of parity information generation elements is configured to be enabled in response to said retention signal.

20. Apparatus as claimed in claim 1 , comprising a plurality of scan paths and a plurality of parity paths.

21. Apparatus as claimed in claim 20 , comprising a first set of parity paths and a second set of parity paths, wherein a parity path of said first set of parity paths provides a first output parity value which is dependent on a first set of state values, and wherein output values of more than one parity path of said second set of parity paths are dependent on said first set of state values.

22. Apparatus as claimed in claim 21 , wherein said first set of parity paths and said second set of parity paths are arranged such that an inverting node at which said respective state value has inverted can be identified by reference to which output values of said first set of parity paths and said second set of parity paths have inverted.

23. Apparatus as claimed in claim 21 , wherein inputs of parity information generation elements of said second set of parity paths are coupled to said plurality of scan paths.

24. Apparatus as claimed in claim 21 , wherein inputs of parity information generation elements of said second set of parity paths are coupled to said first set of parity paths.

25. Apparatus as claimed in claim 1 , further comprising monitor circuitry configured to monitor said output parity value and to initiate a recovery procedure when said output parity value inverts.

26. Apparatus as claimed in claim 25 , wherein said recovery procedure comprises reloading said respective state values held at said respective nodes by said state retention circuits.

27. Apparatus as claimed in claim 22 , further comprising monitor circuitry configured to monitor said output parity value to initiate a recovery procedure when said output parity value inverts, wherein said recovery procedure comprises reloading said respective state values held at said respective nodes by said state retention circuits, and wherein said recovery procedure comprises scanning out a set of state values from a scan path corresponding to said inverting node, re-inverting said respective state value which has inverted, and scanning in said set of state values to said scan path corresponding to said inverting node.

28. Apparatus as claimed in claim 26 , wherein said recovery procedure comprises reloading said respective state values from a previously stored set of state values.

29. Apparatus as claimed in claim 25 , wherein said recovery procedure comprises a reset procedure.

30. Apparatus for processing data comprising: data processing means for performing data processing operations; a plurality of state retention means forming part of said data processing means, said plurality of state retention means for holding respective state values at respective nodes of said data processing means when said data processing means enters a low power mode; a scan path means connecting said plurality of state retention means together in series, said scan path means for scanning said state values into and out of said respective nodes when said data processing means is in a scan mode; and a plurality of parity information generation means, coupled to said scan path, for generating parity information indicative of said respective state values held at said respective nodes by said state retention means, wherein said plurality of parity information generation means are arranged to provide a parity path, such that an output parity value generated at an output of said parity path will invert if one of said respective state values changes, wherein said plurality of parity information generation means are provided with a parity element voltage supply which is configured to keep said parity information generation means active with a full or reduced supply voltage when said data processing means enters said low power mode and when said data processing circuitry is in said scan mode, and wherein said parity element voltage supply is configured to reduce or switch off the power supplied to said parity information generation means when said data processing means performs data processing operations not in said scan mode.

31. A method of configuring apparatus for processing data comprising the steps of: providing data processing circuitry configured to perform data processing operations; providing a plurality of state retention circuits forming part of said data processing circuitry, said plurality of state retention circuits configured to hold respective state values at respective nodes of said data processing circuitry when said data processing circuitry enters a low power mode; connecting, in a scan mode of said data processing circuitry, said plurality of state retention circuits together in series as a scan path, such that said state values may be scanned into and out of said respective nodes; and coupling a plurality of parity information generation elements to said scan path, said plurality of parity information generation elements configured to generate parity information indicative of said respective state values held at said respective nodes by said state retention circuits, wherein said plurality of parity information generation elements are arranged to provide a parity path, such that an output parity value generated at an output of said parity path will invert if one of said respective state values changes, wherein said plurality of parity information generation elements are provided with a parity element voltage supply that keeps said parity information generation elements active with a full or reduced supply voltage when said data processing circuitry enters said low power mode and when said data processing circuitry is in said scan mode, and wherein said parity element voltage supply reduces or switches off the power supplied to said parity information generation elements when said data processing circuitry performs data processing operations not in said scan mode.

32. The method as claimed in claim 31 , wherein said method forms part of an electronic design automation process.

33. The method as claimed in claim 31 , wherein said method further comprises, after said step of providing a plurality of state retention circuits and before said step of connecting said plurality of state retention circuits together in series as a scan path, a step of: providing said plurality of parity information generation elements, each parity information generation element being associated with an adjacent state retention circuit.

34. The method as claimed in claim 31 , wherein said method further comprises a step of performing a timing optimization process on said scan path, said timing optimization process comprising: determining if a signal propagation time for a scan path segment between a first state retention circuit and a second retention circuit satisfies a predetermined criterion; and if said signal propagation time does not satisfy said predetermined criterion, providing at least one hold time fixing buffer on said scan path segment.

35. A computer program product storing in a non-transient fashion a computer program, which when executed on a computing device causes the computing device to generate a representation of the apparatus according to claim 1 .

36. A computer program product storing in a non-transient fashion a computer program, which when executed on a computing device causes the computing device to carry out the method according to claim 31 .