Active Calibration for High-Speed Memory Devices

1. A method for calibrating timing for write operations between a memory controller and a memory device, the method comprising: identifying a time gap required to transition from writing data from the memory controller to the memory device to reading data from the memory device to the memory controller; transmitting a data signal containing a test data pattern from the memory controller to the memory device within the time gap; using a timing signal to receive the test data pattern at the memory device; and using the received test data pattern to calibrate a phase relationship between the data signal and the timing signal during write operations.

2. The method of claim 1 , wherein using the timing signal to receive the test data pattern involves sampling the test data pattern using the timing signal to produce a sampled version of the test data pattern.

3. The method of claim 2 , wherein a phase relationship between the timing signal and the test data pattern is offset by approximately one-half of a symbol time with respect to a phase relationship between the timing signal and a regular write data pattern.

4. The method of claim 2 , wherein using the received test data pattern to calibrate the phase relationship between the data signal and the timing signal involves: returning the sampled version of the test data pattern from the memory device to the memory controller; and calibrating the phase relationship between the data signal and the timing signal based on the sampled version of the test data pattern received at the memory controller.

5. The method of claim 4 , wherein calibrating the phase relationship between the data signal and the timing signal involves computing a phase error indicator based on the sampled version of the test data pattern, wherein the phase error indicator indicates if the data is early or late with respect to the timing signal, wherein computing the phase error involves: comparing a value in the sampled version of the test data pattern with a corresponding preceding value and a corresponding succeeding value in the test data pattern to determine first and second comparison results; and computing a phase error indicator based on the first and second comparison results.

6. The method of claim 4 , wherein returning the sampled version of the test data pattern from the memory device to the memory controller involves returning the sampled version of the test data pattern within the same time gap which was used to transmit the test data pattern.

7. The method of claim 4 , wherein returning the sampled version of the test data pattern from the memory device to the memory controller involves returning the sampled version of the test data pattern within a subsequent time gap following the one which was used to transmit the test data pattern.

8. The method of claim 1 , wherein the method further comprises: receiving multiple copies of the test data pattern from the memory controller at the memory device over a number of time gaps; at the memory device, sampling the multiple copies of the received test data pattern using the timing signal to produce multiple sampled versions of the test data patterns; averaging the multiple sampled versions of the test data patterns to produce an averaged sampled version of the test data pattern; returning the averaged sampled version of the test data pattern from the memory device to the memory controller; receiving the averaged sampled version of the test data pattern at the memory controller; computing a phase error indicator based on the averaged sampled version of the test data pattern, wherein the phase error indicator indicates if the data is early or late with respect to the timing signal; and calibrating the phase relationship between the data signal and the timing signal transmitted from the memory controller to the memory device based on the phase error indicator.

9. The method of claim 8 , wherein returning the averaged sampled version of the test data pattern from the memory device to the memory controller involves returning the averaged sampled version of the test data pattern within a subsequent time gap required to transition from a writing operation to a read operation.

10. A system that calibrates timing for write operations between a memory controller and a memory device, comprising: the memory controller; the memory device; wherein the memory controller is configured to transmit a data signal containing a test data pattern from the memory controller to the memory device within a time gap required to transition from writing data from the memory controller to the memory device to reading data from the memory device to the memory controller; receiving circuitry on the memory device configured to use a timing signal to receive the test data pattern at the memory device; and calibration circuitry on the memory device configured to use the received test data pattern to calibrate a phase relationship between the data signal and the timing signal.

11. The system of claim 10 , wherein the receiving circuitry on the memory device includes an edge sampler configured to sample the test data pattern using the timing signal to produce a sampled version of the test data pattern.

12. The system of claim 11 , further comprising: loopback circuitry on the memory device configured to return the sampled version of the test data pattern from the memory device to the memory controller; and calibration circuitry on the memory controller configured to calibrate the phase relationship between the data signal and the timing signal based on the sampled version of the test data pattern.

13. The system of claim 12 , wherein the calibration circuitry includes computing circuitry to compute a phase error indicator based on the sampled version of the test data pattern, wherein the phase error indicator indicates if the data is early or late with respect to the timing signal, wherein the computing circuitry is configured to compute the phase error indicator by: comparing a value in the sampled version of the test data pattern with a corresponding preceding value and a corresponding succeeding value in the test data pattern to determine first and second comparison results; and computing a phase error indicator based on the first and second comparison results.

14. The system of claim 12 , wherein the loopback circuitry on the memory device is configured to return the sampled version of the test data pattern within the same time gap which was used to transmit the test data pattern.

15. The system of claim 12 , wherein the loopback circuitry on the memory device is configured to return the sampled version of the test data pattern within a subsequent time gap following the one which was used to transmit the test data pattern.

16. The system of claim 10 wherein a phase relationship between the timing signal and the test data pattern is offset by approximately one-half of a bit time with respect to a phase relationship between the timing signal and a regular write data pattern.

17. The system of claim 10 , wherein the memory device is further configured to: receive multiple copies of a test data pattern from the memory controller at the memory device over a number of time gaps; sample the multiple copies of the received test data pattern using the timing signal to produce multiple sampled versions of the test data patterns; average the multiple sampled versions of the test data patterns to produce an averaged sampled version of the test data pattern; and return the averaged sampled version of the test data pattern from the memory device to the memory controller; and wherein the memory controller is further configured to: receive the averaged sampled version of the test data pattern at the memory controller; compute a phase error indicator based on the averaged sampled version of the test data pattern, wherein the phase error indicator indicates if the data is early or late with respect to the timing signal; and calibrate the phase relationship between the timing signal and the data transmitted from the memory controller to the memory device based on the phase error indicator.

18. The system of claim 17 , wherein the memory device returns the averaged sampled version of the test data pattern to the memory controller within a subsequent time gap required to transition from a writing operation to a read operation.