Systems and Methods for Using Reserved Solid State Nonvolatile Memory Storage Capacity for System Reduced Power State

1. A method of storing information on solid state nonvolatile memory, the method comprising: providing an information handling system comprising: solid state nonvolatile memory, and volatile memory configured to only store data when power is provided to the volatile memory; providing power to the volatile memory during a first higher power state of the information handling system; storing system working state information in the volatile memory while the information handling system is in the first higher power state with power provided to the volatile memory; allocating a first space of the solid state nonvolatile memory for storage of saved data and reserving a second space of the solid state nonvolatile memory for data garbage collection during the first higher power state of the information handling system, the first space of the solid state nonvolatile memory being different than the second space of the solid state nonvolatile memory; depowering the volatile memory during a second lower power state of the information handling system with no power provided to the volatile memory; and writing a last system working state information from the powered volatile memory to the reserved second space of the solid state nonvolatile memory for storage prior to depowering the volatile memory during the second lower power state of the information handling system in which no power is provided to the volatile memory.

2. The method of claim 1 , further comprising repowering the volatile memory to restore the information handling system to the first higher power state; and reading the stored system working state information from the reserved second space of the solid state nonvolatile memory and writing the read system working state information back to the volatile memory after repowering the volatile memory to restore the last system working state information of the information handling system.

3. The method of claim 2 , further comprising erasing the stored system working state information from the reserved second space of the solid state nonvolatile memory immediately after reading the stored system working state information from the reserved second space of the solid state nonvolatile memory for writing back to the repowered volatile memory.

4. The method of claim 1 , where the system working state information comprises data and instructions.

5. The method of claim 1 , where the first higher power state of the information handling system comprises an Advanced Configuration and Power Interface (ACPI) S0 power state; and where the second lower power state of the information handling system comprises ACPI S4 power state.

6. The method of claim 1 , further comprising storing data for future recovery in the first space of the solid state nonvolatile memory allocated for storage of saved data during the first higher power state of the information handling system; and storing no data for future recovery in the second space of the solid state nonvolatile memory during the first higher power state of the information handling system.

7. The method of claim 6 , further comprising erasing or pre-erasing all data contained in the second space of the solid state nonvolatile memory during the higher power working state of the information handling system.

8. The method of claim 1 , where the information handling system is not configured to implement a low power state in which the volatile memory remains powered.

9. The method of claim 1 , where the step of writing the system working state information from the powered volatile memory to the reserved second space of the solid state nonvolatile memory further comprises directly using the reserved second space of the solid state nonvolatile memory by writing the system working state information from the powered volatile memory to the reserved second space of the solid state nonvolatile memory without remapping logical blocks of the reserved second space to physical memory blocks of the solid state nonvolatile memory.

10. An information handling system, comprising: solid state nonvolatile memory; volatile memory; and one or more processing devices configured to cause implementation of the following actions: provide power to the volatile memory during a first higher power state of the information handling system, store system working state information in the volatile memory while the information handling system is in the first higher power state with power provided to the volatile memory, allocate a first space of the solid state nonvolatile memory for storage of saved data and reserve a second space of the solid state nonvolatile memory for data garbage collection during the first higher power state of the information handling system, the first space of the solid state nonvolatile memory being different than the second space of the solid state nonvolatile memory, depower the volatile memory during a second lower power state of the information handling system, and write a last system working state information from the powered volatile memory to the reserved second space of the solid state nonvolatile memory for storage prior to depowering the volatile memory during the second lower power state of the information handling system in which no power is provided to the volatile memory.

11. The system of claim 10 , where the one or more processing devices are further configured to cause implementation of the following actions: repower the volatile memory to restore the information handling system to the first higher power state; and read the stored system working state information from the reserved second space of the solid state nonvolatile memory and write the read system working state information back to the volatile memory after repowering the volatile memory to restore the last system working state information of the information handling system.

12. The system of claim 11 , where the one or more processing devices are further configured to cause implementation of the following actions: erase the stored system working state information from the reserved second space of the solid state nonvolatile memory immediately after reading the stored system working state information from the reserved second space of the solid state nonvolatile memory for writing back to the repowered volatile memory.

13. The system of claim 10 , where the system working state information comprises data and instructions.

14. The system of claim 10 , where the first higher power state of the information handling system comprises an Advanced Configuration and Power Interface (ACPI) S0 power state; and where the second lower power state of the information handling system comprises ACPI S4 power state.

15. The system of claim 10 , where the one or more processing devices are further configured to cause implementation of the following actions: store the saved data for future recovery in the first space of the solid state nonvolatile memory allocated for storage of saved data during the first higher power state of the information handling system; and store no data for future recovery in the second space of the solid state nonvolatile memory during the first higher power state of the information handling system.

16. The system of claim 15 , where the one or more processing devices are further configured to cause implementation of the following actions: erase or pre-erase all data contained in the second space of the solid state nonvolatile memory during the first higher power state of the information handling system.

17. The system of claim 10 , where the information handling system is not configured to implement a low power state in which the volatile memory remains powered.

18. The system of claim 10 , where the one or more processing devices are further configured to cause implementation of the following actions: directly use the reserved second space of the solid state nonvolatile memory by writing the system working state information from the powered volatile memory to the reserved second space of the solid state nonvolatile memory by writing the system working state information from the powered volatile memory to the reserved second space of the solid state nonvolatile memory without remapping logical blocks of the reserved second space to physical memory blocks of the solid state nonvolatile memory.

19. The method of claim 1 , further comprising using a write restriction to prevent writing to the reserved second space of the solid state nonvolatile memory during the first higher power state; and using a reserved space write command when entering the second lower power state of the information handling system to disable the write restriction to allow writing of the last system working state information from the powered volatile memory to the reserved second space of the solid state nonvolatile memory when the information handling system is entering the second lower power state.

20. The method of claim 9 , further comprising: performing the following steps during the first higher power state of the information handling system: assigning a first portion of logical memory blocks and their corresponding mapped physical memory blocks to the second space of the solid state nonvolatile memory reserved for data garbage collection during the first higher power state of the information handling system, assigning a second and different portion of logical memory blocks and their corresponding mapped physical memory blocks to the allocated first space of the solid state nonvolatile memory for storage of saved data during the first higher power state of the information handling system, and saving data to the allocated first space of the solid state nonvolatile memory during the first higher power state of the information handling system; then performing the following steps when entering the second lower power state of the information handling system from the first higher power state of the information handling system and prior to depowering the volatile memory: utilizing the first logical memory blocks of the reserved second space together with their same corresponding mapped physical memory blocks to write without remapping the last system working state information from the powered volatile memory to the previously reserved second space of the solid state nonvolatile memory when the information handling system is entering the second lower power state, and assigning the saved data stored in the allocated first space of the solid state nonvolatile memory as quiescent storage while the information handling system remains in the second lower power state; and then depowering the volatile memory during the second lower power state of the information handling system with no power provided to the volatile memory.

21. The method of claim 20 , further comprising performing the following steps when entering the first higher power state of the information handling system from the second lower power state of the information handling system: repowering the volatile memory to restore the information handling system to the first higher power state; then reading the stored last system working state information from given physical memory blocks of the reserved second space of the solid state nonvolatile memory and writing the read system working state information back to the volatile memory after repowering the volatile memory to restore the last system working state information of the information handling system; and then immediately erasing each given physical memory block of the reserved second space of the solid state nonvolatile memory after the stored last system working state information is read from that given physical memory block; then immediately reassigning the first portion of logical memory blocks and their corresponding mapped physical memory blocks to the second space of the solid state nonvolatile memory reserved for data garbage collection; and reassigning the allocated first space of the solid state nonvolatile memory from quiescent storage to active available storage space that is allocated for storage of saved data while the information handling system is in the first higher power state.

22. The system of claim 10 , where the one or more processing devices are further configured to cause implementation of the following actions: use a write restriction to prevent writing to the reserved second space of the solid state nonvolatile memory during the first higher power state; and use a reserved space write command when entering the second lower power state of the information handling system to disable the write restriction to allow writing of the last system working state information from the powered volatile memory to the reserved second space of the solid state nonvolatile memory when the information handling system is entering the second lower power state.

23. The system of claim 18 , where the one or more processing devices are further configured to cause implementation of the following actions: perform the following steps during the first higher power state of the information handling system: assigning a first portion of logical memory blocks and their corresponding mapped physical memory blocks to the reserved second space of the solid state nonvolatile memory reserved for data garbage collection during the first higher power state of the information handling system, assigning a second and different portion of logical memory blocks and their corresponding mapped physical memory blocks to the allocated first space of the solid state nonvolatile memory for storage of saved data during the first higher power state of the information handling system, and saving data to the allocated first space of the solid state nonvolatile memory during the first higher power state of the information handling system; and then perform the following steps when entering the second lower power state of the information handling system from the first higher power state of the information handling system and prior to depowering the volatile memory: utilizing the first logical memory blocks of the reserved second space together with their same corresponding mapped physical memory blocks to write without remapping the last system working state information from the powered volatile memory to the previously reserved second space of the solid state nonvolatile memory when the information handling system is entering the second lower power state, and assigning the saved data stored in the allocated first space of the solid state nonvolatile memory as quiescent storage while the information handling system remains in the second lower power state; and then depowering the volatile memory during the second lower power state of the information handling system with no power provided to the volatile memory.

24. The system of claim 23 , where the one or more processing devices are further configured to cause implementation of the following actions when entering the first higher power state of the information handling system from the second lower power state of the information handling system: repowering the volatile memory to restore the information handling system to the first higher power state; then reading the stored last system working state information from given physical memory blocks of the reserved second space of the solid state nonvolatile memory and writing the read system working state information back to the volatile memory after repowering the volatile memory to restore the last system working state information of the information handling system; and then immediately erasing each given physical memory block of the reserved second space of the solid state nonvolatile memory after the stored last system working state information is read from that given physical memory block; then immediately reassigning the first portion of logical memory blocks and their corresponding mapped physical memory blocks to the second space of the solid state nonvolatile memory reserved for data garbage collection; and reassigning the allocated first space of the solid state nonvolatile memory from quiescent storage to active available storage space that is allocated for storage of saved data while the information handling system is in the first higher power state.