Liquid Crystal Display and Method of Updating Software

1. A liquid crystal display device comprising: a liquid crystal display panel including a plurality of data lines and a plurality of gate lines crossing each other; a backlight unit that radiates backlight to the liquid crystal display panel; a backlight driving circuit that turns on and off light sources of the backlight unit according to backlight dimming data; a data driving circuit that converts digital video data into positive and negative data voltages and supplying the positive and the negative data voltages to the plurality of data lines; a gate driving circuit that supplies a gate pulse to the plurality of gate lines sequentially; a timing controller including a processor configured to execute at least one software that modulates the digital video data to be supplied to the data driving circuit, such that the modulated digital video data enhances pixel contrast and reduces power consumption of the backlight unit, and selects the backlight dimming data according to gain values proper to global dimming and local dimming, and a timing control signal generator configured to generate timing control signals to control operating timings of the data driving circuit and the gate driving circuit; and a host computer configured to supply the digital video data and external timing control signals to the timing controller, wherein the processor operates regardless of the external timing control signals, and includes at least one of a Micro Control Unit (MCU) and a Digital Signal Processor (DSP), and wherein the timing controller further includes: a built-in memory that restores data from the non-volatile memory when power is turn on; a memory controller configured to control reading and writing operations of the built-in memory; an interface receiving circuit configured to receive the digital video data and the external timing control signals from the host computer; an interface transmitting circuit configured to send the digital video data modulated by the processor to the data driving circuit; and a bus controller configured to connect the plurality of data lines supplied with the digital video data received from the interface receiver to one of the processor, the built-in memory, and the interface receiver, selectively.

2. The device according to the claim 1 , wherein the timing control signal generator generates timing control signals that control the operating timings of the data driving circuit and the gate driving circuit using the external timing control signals.

3. The device according to the claim 2 , further comprising a non-volatile memory configured to store the software, parameters required for the software, and pulse information of the timing control signals.