Systems and Methods for Data Detection Including Dynamic Scaling

1. A data processing system, the system comprising: a channel detector circuit, the channel detector circuit including: a branch metric calculator circuit operable: to receive a number of violated checks from a preceding stage, and to scale an intrinsic branch metric using a scalar selected based at least in part on the number of violated checks to yield a scaled intrinsic branch metric; and an intrinsic LLR calculator circuit operable to receive the scaled intrinsic branch metric and to calculate an intrinsic LLR output.

2. The system of claim 1 , wherein the preceding stage is a decoder circuit, and wherein the number of violated checks corresponds to a number of inaccurate outputs provided by the decoder circuit.

3. The system of claim 1 , wherein the scalar is selected as a first value when the number of violated checks is less than a threshold value, and wherein the scalar is selected as a second value when the number of violated checks is not less than the threshold value.

4. The system of claim 3 , wherein the threshold value is programmable.

5. The system of claim 3 , wherein the first value is less than unity, and wherein the second value is unity.

6. The system of claim 3 , wherein the first value is programmable.

7. The system of claim 3 , wherein the second value is programmable.

8. The system of claim 1 , wherein the channel detector circuit further includes: an extrinsic LLR calculator circuit operable to receive the intrinsic LLR output and to calculate an extrinsic output.

9. The system of claim 1 , wherein the system further comprises a decoder circuit, and wherein the decoder circuit is operable to provide a soft output and the number of violated checks to the channel detector circuit.

10. The system of claim 9 , wherein the decoder circuit is operable to receive an output from the channel detector circuit, and wherein the soft output and the number of violated checks are determined based at least in part on the output from the channel detector circuit.

11. The data processing system of claim 1 , wherein the data processing system is implement as part of a storage device.

12. The data processing system of claim 1 , wherein the data processing system is implemented as part of an integrated circuit.

13. A method for dynamically scaling an intrinsic branch metric, the method comprising: receiving a number of violated checks from a preceding stage; determining whether the number of violated checks is less than a threshold value; calculating an intrinsic branch metric; scaling the intrinsic branch metric using a scaling value selected based at least in part upon whether the number of violated checks is less than the threshold value; and wherein a first value less than unity is selected when the number of violated checks is less than the threshold value, and a second value is selected when the number of violated checks is greater than the threshold value.

14. The system of claim 13 , wherein the first value is programmable.

15. The method of claim 13 , wherein the threshold value is programmable.

16. The method of claim 13 , wherein the second value is unity.

17. A storage system, the storage system comprising: a storage medium; a read channel circuit, wherein the read channel circuit is operable to receive data derived from the storage medium, and wherein the read channel circuit includes: a channel detector circuit, wherein the channel detector circuit includes: a branch metric calculator circuit, wherein the branch metric calculator circuit is operable to receive a number of violated checks from a preceding stage, and wherein the branch metric calculator circuit is further operable to scale an intrinsic branch metric using a scalar selected based at least in part on the number of violated checks to yield a scaled intrinsic branch metric; and an intrinsic LLR calculator circuit operable to receive the scaled intrinsic branch metric and to calculate an intrinsic LLR output.

18. The storage system of claim 17 , wherein the preceding stage is a decoder circuit included in the read channel circuit, and wherein the decoder circuit is operable to provide a soft output and the number of violated checks to the channel detector circuit.

19. The storage system of claim 17 , wherein the channel detector circuit further includes: an extrinsic LLR calculator circuit operable to receive the intrinsic LLR output and to calculate an extrinsic output.

20. The storage system of claim 17 , wherein the scalar is selected as a first value when the number of violated checks is less than a threshold value, wherein the scalar is selected as a second value when the number of violated checks is not less than the threshold value, and wherein the threshold value is programmable.