System and Method for Across-Chip Thermal and Power Management in Stacked Ic Designs

1. A computer implemented method comprising: accessing a three-dimensional integrated circuit (3D-IC) model stored in a tangible, non-transitory machine readable medium, the model representing a 3D-IC design to be fabricated and to be operated under a condition, the 3D-IC design comprising: a plurality of elements in a stack configuration; inputting a power profile in a computer processor, the power profile being a function of an operating time and applied to the plurality of elements in the 3D-IC design to be operated under the condition; generating a transient temperature profile in the computer processor based on the 3D-IC model, the transient temperature profile including temperatures at a plurality of points of the 3D-IC design as a function of an operating time, based on the 3D-IC design operating under the power input and the condition, wherein each of the plurality of elements in the 3D-IC design is represented as a thermal resistance-capacitance (RC) unit; identifying a potential thermal violation at a corresponding operating time interval and a corresponding location of the plurality of points based on the 3D-IC design; outputting data representing the potential thermal violation at the corresponding operating time interval and the corresponding location in the 3D-IC design; and changing the power profile as a function of the operating time input in the computer processor, based on the data representing the potential thermal violation at the corresponding operating time interval and the corresponding location in the 3D-IC design.

2. The method of claim 1 , wherein generating a transient temperature profile based on the 3D-IC model comprises: performing a finite element analysis on each of the plurality of points in the 3D-IC design based on a thermal resistance-capacitance (RC) network model.

3. The method of claim 2 , further comprising: inputting a set of boundary conditions as the condition under which the 3D-IC design is to be operated, before performing the finite element analysis.

4. The method of claim 1 , wherein changing the power profile comprises changing a time for turning on or off at least one of the plurality of elements in the 3D-IC design.

5. The method of claim 1 , wherein changing the power profile comprises changing a power level to be applied on at least one of the plurality of elements in the 3D-IC design.

6. The method of claim 1 , wherein the changing the power profile comprises changing a time for turning on or off at least one of the plurality of elements in the 3D-IC design, and changing a power level to be applied on at least one of the plurality of elements in the 3D-IC design.

7. The method of claim 1 , further comprising: changing the 3D-IC design to mitigate the potential thermal violation.

8. The method of claim 7 , further comprising: outputting from the processor the changed 3D-IC design to a non-transitory storage medium, for fabricating a set of photomasks for the 3D-IC design.

9. The method of claim 7 , wherein the 3D-IC design is changed by changing the stack configuration of the plurality of elements comprising two or more IC chips and interposers in the 3D-IC design.

10. The method of claim 7 , wherein the 3D-IC design is changed by changing a package in the 3D-IC design.

11. A computer implemented method comprising: accessing a three-dimensional integrated circuit (3D-IC) model stored in a tangible, non-transitory machine readable medium, the model representing a 3D-IC design to be fabricated and to be operated under a condition, the 3D-IC design comprising: a plurality of elements in a stack configuration; inputting a power profile in a computer processor, the power profile being a function of an operating time and applied to the plurality of elements in the 3D-IC design to be operated under the condition; generating a transient temperature profile in the computer processor based on the 3D-IC model, the transient temperature profile including temperatures at a plurality of points of the 3D-IC design as a function of an operating time, based on the 3D-IC design operating under the power input and the condition, wherein each of the plurality of elements in the 3D-IC design is represented as a thermal resistance-capacitance (RC) unit; identifying a potential thermal violation at a corresponding operating time interval and a corresponding location of the plurality of points based on the 3D-IC design; changing the power profile as a function of the operating time to mitigate the potential thermal violation, based on the data representing the potential thermal violation at the corresponding operating time interval and the corresponding location in the 3D-IC design; and changing the 3D-IC design to mitigate the potential thermal violation.

12. The method of claim 11 , wherein: the transient temperature profile is a response of the power profile as a function of the operating time in a non-steady state.

13. The method of claim 11 , wherein generating a transient temperature profile based on the 3D-IC model comprises: inputting a set of boundary conditions as the condition under which the 3D-IC design is to be operated; and performing a finite element analysis on each of the plurality of points in the 3D-IC design based on a thermal resistance-capacitance (RC) network model.

14. The method of claim 11 , further comprising: outputting from the processor the changed 3D-IC design to a non-transitory storage medium for fabricating a set of photomasks for the 3D-IC design.

15. A computer implemented system comprising: one or more processors; and at least one tangible, non-transitory machine readable medium encoded with one or more programs, to be executed by the one or more processors, to perform steps of: accessing a three-dimensional integrated circuit (3D-IC) model stored in a tangible, non-transitory machine readable medium, the model representing a 3D-IC design to be fabricated and to be operated under a condition, the 3D-IC design comprising: a plurality of elements in a stack configuration; inputting a power profile in a computer processor, the power profile being a function of an operating time and applied to the plurality of elements in the 3D-IC design to be operated under the condition; generating a transient temperature profile in the computer processor based on the 3D-IC model, the transient temperature profile including temperatures at a plurality of points of the 3D-IC design as a function of an operating time, based on the 3D-IC design operating under the power input and the condition, wherein each of the plurality of elements in the 3D-IC design is represented as a thermal resistance-capacitance (RC) unit; identifying a potential thermal violation at a corresponding operating time interval and a corresponding location of the plurality of points based on the 3D-IC design; outputting data representing the potential thermal violation at the corresponding operating time interval and the corresponding location in the 3D-IC design, and changing the power profile as a function of the operating time to mitigate the potential thermal violation.

16. The system of claim 15 , wherein generating a transient temperature profile based on the 3D-IC model comprises: inputting a set of boundary conditions as the condition under which the 3D-IC design is to be operated; and performing a finite element analysis on each of the plurality of point in the 3D-IC design based on a thermal resistance-capacitance (RC) network model.

17. The system of claim 15 , wherein the functions of the one or more programs further comprise: changing the 3D-IC design comprising the plurality of the elements and a package in the 3D-IC design to mitigate the potential thermal violation.