Method and Apparatus for Executing a Program by an Spi Interface Memory

1. A multi-channel SPI interface memory controller, disposed between a central processing unit (CPU) and a multi-channel serial peripheral interface (SPI) interface memory, comprising: a data path interface coupled to a bus of the CPU; a control path interface coupled to the bus of the CPU; a master controller coupled to the multi-channel SPI interface memory; and a register bank disposed between the master controller and the control path interface, wherein the master controller is in signal coupling with the data path interface, and in signal coupling through the register bank with the control path interface, wherein the master controller comprises a main state machine, wherein the main state machine has six logical states: idle, instruction, address, dummy, wait, and data, wherein the master controller controls the main state machine to transition to one of the six logical states after parsing an instruction in the register bank.

2. The multi-channel SPI interface memory controller of claim 1 , wherein the state machine further has a seventh state: data_ 1 state, wherein when a massive data read/write operation is conducted by the multi-channel SPI interface memory controller, the state machine transitions between the data state and the data_ 1 state alternatively until the massive data read/write operation completes.

3. The multi-channel SPI interface memory controller of claim 1 , wherein an encrypt/decrypt module is disposed between the data path interface and the master controller, for encrypting data to be written into the multi-channel SPI interface memory and for decrypting data read from the multi-channel SPI interface memory.

4. The multi-channel SPI interface memory controller of claim 3 , wherein the register bank is coupled to the encrypt/decrypt module for controlling the ON or OFF of the encrypt/decrypt module.

5. The multi-channel SPI interface memory controller of claim 1 , wherein the master controller further comprises: a data/address buffer, a data reception module, an instruction/data sending module, and a codec logic, wherein instruction information from the register bank goes into the main state machine after decoding by the codec logic, wherein the data reception module performs control feedback to the main state machine, and is coupled to the SPI interface memory so as to store data or memory operation parameters read from the SPI interface memory into the data/address buffer, and to send the data or memory operation parameters from the data/address buffer to the CPU; and wherein the instruction/data sending module performs control feedback to the main state machine, and writes write data from the data path interface or the memory operation parameters from the register bank into the multi-channel SPI interface memory through the data/address buffer.

6. A method for controlling a multi-channel serial peripheral interface (SPI) interface memory controller, the multi-channel SPI interface memory controller being disposed between a central processing unit (CPU) and a multi-channel SPI interface memory and comprising a master controller coupled to the multi-channel SPI interface memory, the master controller comprising a main state machine, wherein the method comprises: providing a data path and a control path between the CPU and the multi-channel SPI interface memory controller, respectively, wherein the main state machine is provided with six logical states: idle, instruction, address, dummy, wait, and data, wherein the master controller controls the main state machine to transition to one of the six logical states according to a received instruction.

7. The method of claim 6 , wherein the state machine is further provided with a seventh state: data_ 1 state, wherein when a massive data read/write operation is conducted by the multi-channel SPI interface memory controller, the state machine is transitioned between the data state and the data_ 1 state alternatively until the massive data read/write operation completes.