Dual Rail Power Supply Scheme for Memories

1. A dual rail memory operable at a first voltage and a second voltage, the memory comprising: at least one input circuit operable to receive at least a first input signal referenced to the first voltage and operable to generate a second input signal referenced to the second voltage; at least one output circuit operable to receive at least a first output signal referenced to the second voltage and to generate a second output signal referenced to the first voltage; and a clock generator circuit coupled to the at least one input circuit, the clock generator circuit operable to receive a first clock signal referenced to the first voltage and to generate a second clock signal referenced to the second voltage, a logic state of the second clock signal being a function of a logic state of the first clock signal.

2. The memory of claim 1 , wherein the first voltage is higher than the second voltage.

3. The memory of claim 1 , wherein the first voltage is lower than the second voltage.

4. The memory of claim 1 , wherein the at least one input circuit comprises at least one input receiver.

5. The memory of claim 4 , wherein the at least one input circuit comprises at least one level shifter.

6. The memory of claim 1 , wherein the at least one input circuit comprises at least one level shifter circuit coupled between the at least one input circuit and at least one latch circuit.

7. The memory of claim 1 , wherein the at least one input circuit comprises at least one level shifter circuit coupled in an asynchronous delay path of the at least one input signal.

8. The memory of claim 1 , wherein the at least one output circuit comprises at least one output driver.

9. The memory of claim 8 , wherein the at least one output circuit comprises at least one level shifter circuit.

10. The memory of claim 1 , wherein the at least one input circuit comprises at least one of an address input adapted to receive one or more address signals, a data input adapted to receive one or more data signals, and a control input adapted to receive one or more control signal signals.

11. The memory of claim 1 , wherein the clock generator circuit further comprises: a time-sensitive circuit; a level shifter circuit; and a reset circuit coupled to the time-sensitive circuit and to the level shifter circuit.

12. The memory of claim 11 , further comprising a self-timing circuit operable at the second voltage and operable to send a signal to the reset circuit.

13. The memory of claim 12 , wherein the reset circuit further comprises an input adapted to receive the signal from the self-timing circuit to reset the second clock signal.

14. The memory of claim 1 , wherein at least a portion of the memory is fabricated in at least one integrated circuit.

15. A dual rail memory operable at a first voltage and a second voltage, the memory comprising: an input receiver circuit operable to receive at least a first input signal referenced to the first voltage; at least a first level shifter circuit coupled with the input receiver and operable to generate at least a second input signal referenced to the second voltage, the second input signal having a logic state that is a function of a logic state of the first input signal; an output driver circuit operable to generate at least a first output signal referenced to the first voltage; at least a second level shifter circuit coupled with the output driver circuit and operable to generate at least a second output signal referenced to the second voltage, a logic state of the second output signal being a function of a logic state of the first output signal; a clock generator circuit comprising: a reset circuit; a third level shifter circuit coupled with the reset circuit; and a clock circuit coupled with the reset circuit and the third level shifter circuit, the clock generator circuit having a clock output coupled with the input receiver circuit, the clock generator circuit operable to receive a first clock signal referenced to the first voltage and to generate a second clock signal referenced to the second voltage at the clock output, the second clock signal having a logic state that is a function of a logic state of the first clock signal.

16. The memory of claim 15 , wherein the first voltage is higher than the second voltage.

17. The memory of claim 15 , wherein the first voltage is lower than the second voltage.

18. The memory of claim 15 , further comprising a self-timing circuit operable at the second voltage and operable to send a signal to the reset circuit.

19. The memory of claim 18 , wherein the reset circuit further comprises an input adapted to receive the signal from the self-timing circuit to reset the second clock signal.

20. The memory of claim 15 , wherein the input receiver circuit comprise at least one of an address input adapted to receive one or more address signals, a data input adapted to receive one or more data signals, and a control input adapted to receive one or more control signal signals.

21. The memory of claim 15 , wherein at least a portion of the memory is fabricated in at least one integrated circuit.