Circular Buffer Based Rate Matching

1. A method that facilitates rate matching in a wireless communication environment, comprising: separating systematic bits, parity 1 bits, and parity 2 bits from an encoder into distinct groups; interleaving the systematic bits, the parity 1 bits, and the parity 2 bits within the respective, distinct groups; interlacing the interleaved parity 1 bits with the interleaved parity 2 bits, wherein the interlacing comprises combining the interleaved parity 1 bits with the interleaved parity 2 bits in an alternating manner where each bit in a sequence of the interlaced and interleaved parity 1 and parity 2 bits alternates between being a parity 1 bit and a parity 2 bit; inserting the interleaved systematic bits into a buffer followed by the interlaced and interleaved parity 1 and parity 2 bits; and selecting, in sequential order, the bits inserted into the buffer for transmission.

2. The method of claim 1 , further comprising applying a turbo code to at least one code block to generate at least one encoded block, the at least one encoded block includes the systematic bits, the parity 1 bits, and the parity 2 bits to be separated.

3. The method of claim 1 , wherein the interleaving comprises interleaving the systematic bits together to randomize an ordering of the systematic bits; interleaving the parity 1 bits together to randomize an ordering of the parity 1 bits; and interleaving the parity 2 bits together to randomize an ordering of the parity 2 bits.

4. The method of claim 1 , wherein the inserting comprises inserting all of the interleaved systematic bits into the buffer prior to inserting a first one of the interlaced and interleaved parity 1 and parity 2 bits into the buffer.

5. A method that facilitates rate matching in a wireless communication environment, comprising: applying a turbo code to at least one code block to generate at least one encoded block, the at least one encoded block including systematic bits, parity 1 bits, and parity 2 bits; separating the systematic bits, the parity 1 bits, and the parity 2 bits from the at least one encoded block into distinct groups; collecting all systematic bits from the at least one encoded block into a first group; collecting all parity 1 bits from the at least one encoded block into a second group; collecting all parity 2 bits from the at least one encoded block into a third group; interleaving the systematic bits, the parity 1 bits, and the parity 2 bits within the respective, distinct groups; interlacing the interleaved parity 1 bits with the interleaved parity 2 bits; inserting the interleaved systematic bits into a buffer followed by the interlaced and interleaved parity 1 and parity 2 bits; and selecting, in sequential order, the bits inserted into the buffer for transmission.

6. The method of claim 5 , wherein the interlacing the interleaved parity 1 bits with the interleaved parity 2 bits comprises combining the interleaved parity 1 bits with the interleaved parity 2 bits as a function of a pre-defined pattern.

7. A wireless communications apparatus, comprising: a memory that retains instructions for: separating systematic bits, parity 1 bits, and parity 2 bits from at least one encoded block outputted by an encoder into distinct groups, interleaving the systematic bits together to generate a randomized sequence of systematic bits, interleaving the parity 1 bits together to generate a randomized sequence of parity 1 bits, interleaving the parity 2 bits together to generate a randomized sequence of parity 2 bits, interlacing the randomized sequence of parity 1 bits and the randomized sequence of parity 2 bits to yield an interlaced sequence of parity 1 and 2 bits, wherein the interlacing comprises combining the randomized sequence of parity 1 bits with the randomized sequence of parity 2 bits in an alternating manner where each bit in the interlaced sequence of parity 1 and 2 bits alternates between being a parity 1 bit and a parity 2 bit, inserting the randomized sequence of systematic bits into a buffer followed by the interlaced sequence of parity 1 and 2 bits, and selecting, in sequential order, the bits inserted into the buffer for transmission; and a processor, coupled to the memory, configured to execute the instructions retained in the memory.

8. The wireless communications apparatus of claim 7 , wherein the memory further retains instructions related to selecting at least a portion of the interlaced sequence of parity 1 and 2 bits after selecting all bits of the randomized sequence of systematic bits.

9. The wireless communications apparatus of claim 7 , wherein the memory further retains instructions related to selecting all bits of the randomized sequence of systematic bits prior to selecting a first bit of the interlaced sequence of parity 1 and 2 bits.

10. The wireless communications apparatus of claim 7 , wherein the memory further retains instructions related to applying a turbo code to at least one code block to generate the at least one encoded block, the at least one encoded block includes the systematic bits, the parity 1 bits, and the parity 2 bits to be separated.

11. The wireless communications apparatus of claim 7 , wherein the memory further retains instructions related to inserting all bits in the randomized sequence of systematic bits into the buffer prior to inserting a first bit of the interlaced sequence of parity 1 and 2 bits into the buffer, with a total number of the systematic bits and the parity 1 and 2 bits inserted into the buffer being a function of available space in the buffer or a total number of bits to transmit for the at least one encoded block.

12. The wireless communication apparatus of claim 11 , wherein the memory further retains instructions related to selecting bits inserted into the buffer for transmission and not selecting bits omitted from the buffer.

13. A wireless communications apparatus, comprising: a memory that retains instructions for: applying a turbo code to at least one code block to generate at least one encoded block, the at least one encoded block including systematic bits, parity 1 bits, and parity 2 bits, identifying the systematic bits, the parity 1 bits, and the parity 2 bits from the at least one encoded block, collecting all systematic bits from the at least one encoded block, collecting all parity 1 bits from the at least one encoded block, collecting all parity 2 bits from the at least one encoded block, interleaving the systematic bits together to generate a randomized sequence of systematic bits, interleaving the parity 1 bits together to generate a randomized sequence of parity 1 bits, interleaving the parity 2 bits together to generate a randomized sequence of parity 2 bits, interlacing the randomized sequence of parity 1 bits and the randomized sequence of parity 2 bits to yield an interlaced sequence of parity 1 and 2 bits, inserting the randomized sequence of systematic bits into a buffer followed by the interlaced sequence of parity 1 and 2 bits, and selecting, in sequential order, the bits inserted into the buffer for transmission; and a processor, coupled to the memory, configured to execute the instructions retained in the memory.

14. A wireless communications apparatus that enables employing rate matching in a wireless communication environment, comprising: means for separating systematic bits, parity 1 bits, and parity 2 bits from an encoder into distinct groups; means for interleaving the systematic bits collected from at least one encoded block outputted by an encoder; means for interleaving the parity 1 bits collected from the at least one encoded block; means for interleaving the parity 2 bits collected from the at least one encoded block; means for interlacing the interleaved parity 1 bits and the interleaved parity 2 bits, wherein the means for interlacing combines the interleaved parity 1 bits with the interleaved parity 2 bits in an alternating manner where each bit in a sequence of the interlaced and interleaved parity 1 and parity 2 bits alternates between being a parity 1 bit and a parity 2 bit; means for inserting the interleaved systematic bits into a buffer followed by the interlaced and interleaved parity 1 and parity 2 bits; and means for selecting, in sequential order, the bits inserted into the buffer for transmission.

15. The wireless communications apparatus of claim 14 , further comprising means for generating the at least one encoded block from an inputted at least one code block.

16. The wireless communications apparatus of claim 14 , wherein the means for selecting comprises means for selecting all interleaved systematic bits prior to selecting a first one of the interlaced and interleaved parity 1 and 2 bits.

17. The wireless communications apparatus of claim 14 , further comprising means for transmitting the selected bits over a channel.

18. A wireless communications apparatus that enables employing rate matching in a wireless communication environment, comprising: means for collecting all systematic bits from at least one encoded block; means for collecting all parity 1 bits from the at least one encoded block; means for collecting all parity 2 bits from the at least one encoded block; means for interleaving the systematic bits collected from the at least one encoded block; means for interleaving the parity 1 bits collected from the at least one encoded block; means for interleaving the parity 2 bits collected from the at least one encoded block; means for interlacing the interleaved parity 1 bits and the interleaved parity 2 bits; means for inserting the interleaved systematic bits into a buffer followed by the interlaced and interleaved parity 1 and parity 2 bits; and means for selecting, in sequential order, the bits inserted into the buffer for transmission.

19. The wireless communications apparatus of claim 18 , wherein the means for interlacing comprises means for interlacing the interleaved parity 1 bits and the interleaved parity 2 bits as a function of a pre-defined pattern.

20. A non-transitory machine-readable medium having stored thereon machine-executable instructions for: separating systematic bits, parity 1 bits, and parity 2 bits from at least one encoded block outputted by an encoder into distinct groups; interleaving the systematic bits together to generate a randomized sequence of systematic bits; interleaving the parity 1 bits together to generate a randomized sequence of parity 1 bits; interleaving the parity 2 bits together to generate a randomized sequence of parity 2 bits; interlacing the randomized sequence of parity 1 bits and the randomized sequence of parity 2 bits to yield an interlaced sequence of parity 1 and 2 bits, wherein the interlacing comprises combining the randomized sequence of parity 1 bits with the randomized sequence of parity 2 bits in an alternating manner where each bit in the interlaced sequence of parity 1 and 2 bits alternates between being a parity 1 bit and a parity 2 bit; inserting the randomized sequence of systematic bits into a buffer followed by the interlaced sequence of parity 1 and 2 bits; and selecting, in sequential order, the bits inserted into the buffer for transmission.

21. The non-transitory machine-readable medium of claim 20 , the machine-executable instructions are further for selecting all bits of the randomized sequence of systematic bits prior to selecting a first bit of the interlaced sequence of parity 1 and 2 bits.

22. The non-transitory machine-readable medium of claim 20 , the machine-executable instructions are further for selecting at least a portion of the interlaced sequence of parity 1 and 2 bits after selecting all bits of the randomized sequence of systematic bits.

23. The non-transitory machine-readable medium of claim 20 , the machine-executable instructions are further for applying a turbo code to at least one code block to generate the at least one encoded block, the at least one encoded block includes the systematic bits, the parity 1 bits, and the parity 2 bits to be separated.

24. The non-transitory machine-readable medium of claim 20 , the machine-executable instructions are further for inserting an entirety of the randomized sequence of systematic bits into the buffer prior to inserting a first bit of the interlaced sequence of parity 1 and 2 bits into the buffer, with a total number of the systematic bits and the parity 1 and 2 bits inserted into the buffer being a function of available space in the buffer or a total number of bits to transmit for the at least one encoded block.

25. The non-transitory machine-readable medium of claim 24 , the machine-executable instructions are further for selecting bits inserted into the buffer for transmission and not selecting bits omitted from the buffer.

26. A non-transitory machine-readable medium having stored thereon machine-executable instructions for: applying a turbo code to at least one code block to generate at least one encoded block, the at least one encoded block including systematic bits, parity 1 bits, and parity 2 bits, identifying the systematic bits, the parity 1 bits, and the parity 2 bits from the at least one encoded block; collecting all systematic bits from the at least one encoded block, collecting all parity 1 bits from the at least one encoded block, collecting all parity 2 bits from the at least one encoded block; interleaving the systematic bits together to generate a randomized sequence of systematic bits; interleaving the parity 1 bits together to generate a randomized sequence of parity 1 bits; interleaving the parity 2 bits together to generate a randomized sequence of parity 2 bits; interlacing the randomized sequence of parity 1 bits and the randomized sequence of parity 2 bits to yield an interlaced sequence of parity 1 and 2 bits; inserting the randomized sequence of systematic bits into a buffer followed by the interlaced sequence of parity 1 and 2 bits; and selecting, in sequential order, the bits inserted into the buffer for transmission.

27. In a wireless communications system, an apparatus comprising: a processor configured to: segregate systematic bits, parity 1 bits, and parity 2 bits from at least one encoded block into distinct groups; interleave the systematic bits, the parity 1 bits, and the parity 2 bits within the respective, distinct groups; interlace the interleaved parity 1 bits with the interleaved parity 2 bits by combining the interleaved parity 1 bits with the interleaved parity 2 bits in an alternating manner where each bit in a sequence of the interlaced and interleaved parity 1 and parity 2 bits alternates between being a parity 1 bit and a parity 2 bit; insert the interleaved systematic bits into a buffer followed by the interlaced and interleaved parity 1 and parity 2 bits; and select, in sequential order, the bits inserted into the buffer for transmission.