Data Latch Circuit, Driving Method of the Data Latch Circuit, and Display Device

1. A semiconductor device comprising: a first n-channel transistor; a second n-channel transistor electrically connected to the first n-channel transistor; a first p-channel transistor; a second p-channel transistor; a first transistor; a second transistor; a third transistor; and an inverter, wherein a gate terminal of the second n-channel transistor, a gate terminal of the first p-channel transistor, and a gate terminal of the first transistor are electrically connected to one another, wherein a first terminal of the first p-channel transistor and a first terminal of the second p-channel transistor are electrically connected to a first line, wherein a first terminal of the second n-channel transistor is electrically connected to a second line, wherein a second terminal of the second n-channel transistor is electrically connected to a first terminal of the first n-channel transistor, wherein a second terminal of the first n-channel transistor, a second terminal of the first p-channel transistor, an input terminal of the inverter, and a second terminal of the second p-channel transistor are electrically connected to one another, wherein the second transistor and the third transistor are electrically connected to an output terminal of the inverter, wherein the second transistor is electrically connected to a gate terminal of the second p-channel transistor, wherein the first transistor and the third transistor is electrically connected to a gate terminal of the first n-channel transistor, and wherein the gate terminal of the first n-channel transistor is electrically connected to the gate terminal of the second p-channel transistor through the second transistor.

2. The semiconductor device according to claim 1 , wherein when the first transistor is turned on, the first p-channel transistor is turned on, the second n-channel transistor is turned off, the second transistor and the third transistor are high impedance, and a potential of the first line is supplied to the input terminal of the inverter.

3. The semiconductor device according to claim 1 , wherein when the first transistor is turned off, the first p-channel transistor is turned off, the second n-channel transistor is turned on, a potential to be supplied to the input terminal of the inverter is determined to be a potential of the first line or a potential of the second line depending on a level of an input signal to be inputted to the gate terminal of the first n-channel transistor, and just after that, the second transistor and the third transistor are turned on.

4. The semiconductor device according to claim 1 , wherein a second potential to be supplied to the input terminal of the inverter is held by the first n-channel transistor, the second n-channel transistor, the inverter, and the third transistor, and wherein a first potential to be supplied to the input terminal of the inverter is held by the second p-channel transistor, the inverter, and the second transistor.

5. The semiconductor device according to claim 1 , wherein an amplitude of an input signal is smaller than a potential difference between the first line and the second line.

6. A display device having the semiconductor device according to claim 1 .

7. A mobile phone including a display module having the semiconductor device according to claim 1 .

8. A television device including a display module having the semiconductor device according to claim 1 .

9. A semiconductor device comprising: a first n-channel transistor; a second n-channel transistor electrically connected to the first n-channel transistor; a first p-channel transistor; a second p-channel transistor; a first transistor; a second transistor; an inverter, wherein a gate terminal of the second n-channel transistor, a gate terminal of the first p-channel transistor, and a gate terminal of the first transistor are electrically connected to one another, wherein a first terminal of the first p-channel transistor and a first terminal of the second p-channel transistor are electrically connected to a first line, wherein a first terminal of the second n-channel transistor is electrically connected to a second line, wherein a second terminal of the second n-channel transistor is electrically connected to a first terminal of the first n-channel transistor, wherein a second terminal of the first n-channel transistor, a second terminal of the first p-channel transistor, an input terminal of the inverter, and a second terminal of the second p-channel transistor are electrically connected to one another, wherein the second transistor is electrically connected to an output terminal of the inverter, wherein the second transistor is electrically connected to a gate terminal of the second p-channel transistor, wherein a gate terminal of the first n-channel transistor is electrically connected to the first transistor, and wherein the gate terminal of the first n-channel transistor is electrically connected to the gate terminal of the second p-channel transistor through the second transistor.

10. The semiconductor device according to claim 9 , wherein when the first transistor is turned on, the first p-channel transistor is turned on, the second n-channel transistor is turned off, the second transistor is high impedance, and a potential of the first line is supplied to the input terminal of the inverter.

11. The semiconductor device according to claim 9 , wherein when the first transistor is turned off, the first p-channel transistor is turned off, the second n-channel transistor is turned on, a potential to be supplied to the input terminal of the inverter is determined to be a potential of the first line or a potential of the second line depending on a level of an input signal to be inputted to the gate terminal of the first n-channel transistor and just after that, the second transistor is turned on.

12. The semiconductor device according to claim 9 , wherein a second potential to be supplied to the input terminal of the inverter is held by the first n-channel transistor, the second n-channel transistor and the inverter, and wherein a first potential to be supplied to the input terminal of the inverter is held by the second p-channel transistor, the inverter, and the second transistor.

13. The semiconductor device according to claim 9 , wherein an amplitude of an input signal is smaller than a potential difference between the first line and the second line.

14. A display device having the semiconductor device according to claim 9 .

15. A mobile phone including a display module having the semiconductor device according to claim 9 .

16. A television device including a display module having the semiconductor device according to claim 9 .