Technique for Preserving Cached Information During a Low Power Mode

1. A system comprising: a first processor having at least two processor cores, wherein at least one of the processor cores is to enter a low power mode, in which information stored in a local cache of the at least one processor core is no longer accessible, and a logic to direct an access to the local cache or to a shared cache that is to store versions of information stored in each of the at least two processor cores depending on a power state of the at least one processor core; a second processor having at least one processor core to access information from the shared cache if the at least one processor core of the first processor is in the low power mode; a system memory to store versions of information stored in the shared cache; and a memory controller through which the at least one processor core of the second processor is to access the system memory.

2. The system of claim 1 , further comprising a non-volatile memory to store a power state of the at least one processor core of the first processor.

3. The system of claim 2 , wherein the at least one processor core of the second processor is to attempt to access the information from the at least one processor core of the first processor regardless of the power state in which the at least one processor core of the first processor is in.

4. The system of claim 3 , wherein if the at least one processor core of the first processor has not entered the low power mode, the at least one processor core of the second processor is to snoop the at least one processor core's local cache of the first processor.

5. The system of claim 1 , wherein the first and second processors are coupled via a front-side bus.

6. The system of claim 1 , wherein the first and second processors are coupled via a point-to-point interconnect.

7. The system of claim 1 , wherein the first and second processors are coupled via a ring interconnect.

8. The system of claim 1 , wherein the low power mode includes stopping a clock and removing power to the at least one processor core of the first processor.

9. The system of claim 8 , wherein a lower latency is incurred to access information from the shared cache than to wait for the at least one processor core of the first processor to return from the low power mode and access its local cache.

10. A non-transitory machine-readable medium having stored thereon a set of instructions, which if executed by a machine causes the machine to perform a method comprising: causing a first processor to redirect an access to a second processor or a third processor to a cache shared between at least the second processor and the third processor instead of a local cache corresponding to one of the second and third processors in response to determining that at least one of the second and third processors has entered a low power mode, wherein entering the low power mode causes the at least one of the second and third processors to store information from its respective local cache to the shared cache and to gate a clock to the at least one of the second and third processors and to reduce power to the at least one of the second and third processors to substantially zero.

11. The non-transitory machine-readable medium of claim 10 , wherein the method further comprises determining whether the at least second and third processors are in the low power mode.

12. The non-transitory machine-readable medium of claim 11 , wherein determining includes accessing a storage area containing power state information of the at least second and third processors.

13. The non-transitory machine-readable medium of claim 10 , wherein the low power mode is a core component three (CC3) power state.

14. A processor comprising: a first core including a first local cache, wherein when the first core is to be placed in a low power mode, modified information stored within the first local cache is to be stored in a shared cache prior to entry into the low power mode; a second core coupled to the first core via a ring interconnect and to initiate a snoop to the first core to access information stored within the first local cache; and logic of the first core including a storage to store a power state of the first core and to direct the snoop to either the first local cache or to the shared cache based on a power state of the first core, wherein the logic is to direct the snoop to the first local cache when the first core is active and to the shared cache when the first core is in the low power mode.

15. The processor of claim 14 , wherein the first core is to indicate if it is to enter the low power mode and to direct the access accordingly.

16. The processor of claim 14 , wherein the shared cache is to store at least some information stored within the first local cache and a second local cache associated with the second core.

17. The processor of claim 16 , wherein the first local cache includes a level one (L1) cache and the shared cache includes a level two (L2) cache.

18. The processor of claim 14 , wherein the low power mode includes reduction of at least one clock of the first core and disabling of power to the first core.

19. The processor of claim 14 , wherein the low power mode includes placement of the first core into an idle state and reduction of an operating voltage of the first core to substantially zero.

20. The processor of claim 14 , wherein the first local cache is to be flushed as a result of entering the low power state.