Memory Module Having a Write-Timing Calibration Mode

1. A memory module comprising: a circuit board having a connector interface that enables the circuit board to be removably inserted into an interconnect socket, the circuit board including an address/control signal path, an address/control timing path, a plurality of data signal paths and a plurality of data timing paths; and a plurality of memory components coupled to the address/control signal path at respective, successive points along the length of the address/control signal path such that signal propagation delay on the address/control path progressively increases for successively disposed memory components, each of the memory components being coupled to a respective one of the data signal paths and having: a core of dynamic random access memory cells; first circuitry coupled to the address/control signal path to receive control information that specifies a write operation and coupled to the address/control timing path to receive a clock signal that controls reception of the control information; second circuitry coupled to the respective one of the data signal paths to receive write data corresponding to the write operation and coupled to a respective one of the data timing paths to receive a timing signal indicating that the write data is valid, the second circuitry being operable in a calibration mode to receive multiple delayed versions of the timing signal; and third circuitry to output signals corresponding to the multiple delayed versions of the timing signal to enable determination, in a memory controller, of a delay time between outputting the control information on the address/control signal path and outputting the write data on the respective data signal path, the delay time to compensate for a difference between a propagation time of the control information on the address/control signal path and a propagation time of the write data on the respective data signal path.

2. The memory module of claim 1 wherein the timing signal transitions between signal levels to indicate that the write data is valid, and wherein the timing signal lacks transitions during an interval in which no data is conveyed on the respective data signal path.

3. The memory module of claim 1 wherein the timing signal conveys write timing information for a group of eight write data signals of the write data, and wherein a rising edge transition of the timing signal indicates a valid first symbol of the write data, and a falling edge transition of the timing signal indicates a valid second symbol of the write data.

4. The memory module of claim 1 wherein the first circuitry is additionally to receive, via the address/control signal path, address information that identifies a memory location of the core of dynamic random access memory cells for the write operation.

5. The memory module of claim 4 wherein the clock signal that controls reception of the control information also controls reception of the address information.

6. The memory module of claim 1 wherein the clock signal that controls reception of the control information transitions between signal levels to indicate a time at which the first circuitry is to sample the control information.

7. The memory module of claim 1 wherein the plurality of memory components comprises a plurality of dynamic random access memory (DRAM) components.

8. The memory module of claim 1 wherein the address/control timing path is coupled at respective points along its length to the memory components and routed alongside the address/control path such that signal propagation delay on the address/control timing path is substantially similar to the signal propagation delay on the address/control path.

9. The memory module of claim 1 wherein the data timing paths are routed alongside respective ones of the data signal paths such that propagation delay on each of the data timing paths is substantially similar to signal propagation delay on the respective one of the data signal paths.

10. A method of operation within a memory module having an address/control signal path, an address/control timing path, a plurality of data signal paths, a plurality of data timing paths, and a plurality of memory components coupled in parallel to the address/control signal path and in parallel to the address/control timing path, and coupled respectively to the data signal paths, the method comprising: receiving a clock signal within each of the memory components via the address/control timing path at respective, staggered times corresponding to propagation time differences along the address/control timing path; receiving control information within each of the memory components via the address/control signal path at respective, staggered times indicated by the clock signal, the control information specifying a write operation; receiving a respective timing signal within each of the memory components via a respective one of the data timing paths, including receiving, in a calibration mode, multiple delayed versions of the respective timing signal; receiving write data corresponding to the write operation within each of the memory components via respective one of the data signal paths at times indicated by the respective timing signals; and within each of the memory components, outputting signals corresponding to the multiple delayed versions of the timing signal to enable determination, in a memory controller component, of a delay time between outputting the control information on the address/control signal path and outputting the write data on the respective data signal path, the delay time to compensate for a difference between a propagation time of the control information on the address/control signal path and a propagation time of the write data on the respective data signal path.

11. The method of claim 10 wherein the timing signal transitions between signal levels to indicate that the write data is valid, and wherein the timing signal lacks transitions during an interval in which no data is conveyed on the respective data signal path.

12. The method of claim 10 wherein a rising edge transition of the timing signal indicates a valid first symbol of the write data, and a falling edge transition of the timing signal indicates a valid second symbol of the write data.

13. The method of claim 10 wherein the timing signal conveys write timing information for a group of eight write data signals of the write data.

14. The method of claim 10 further comprising receiving, within each of the memory components via the address/control signal path, address information that identifies a memory location for the write operation.

15. The method of claim 14 wherein the clock signal that controls reception of the control information also controls reception of the address information.

16. The method of claim 10 wherein the clock signal transitions between signal levels to indicate a time at which to sample the control information.

17. The method of claim 10 wherein the memory components comprise a plurality of dynamic random access memory (DRAM) components.

18. The method of claim 10 wherein the address/control timing path is coupled at respective points along its length to the memory components and routed alongside the address/control path such that signal propagation delay on the address/control timing path is substantially similar to the signal propagation delay on the address/control path.

19. The method of claim 10 wherein the data timing paths are routed alongside respective ones of the data signal paths such that propagation delay on each of the data timing paths is substantially similar to signal propagation delay on the respective one of the data signal paths.

20. A method of operation within a memory module having a plurality of memory components, the method comprising: receiving control information within each of the memory components via a shared address/control path, the control information specifying a write operation; receiving respective write data values corresponding to the write operation within each of the memory components via respective data paths; receiving a respective set of delayed versions of a timing signal within each of the memory components, wherein a rising edge transition of each timing signal version indicates a time to sample one of the write data values and a falling edge transition of the timing signal indicates a time to sample another one of the write data values; and outputting, from each of the memory components, signals corresponding to the respective set of delayed versions of the timing signal.