Data Output Circuit Responsive to Calibration Code and on Die Termination Code

1. A data output circuit comprising: a pre-code generation unit configured to generate one of a pre-pull-up code and a pre-pull-down code according to a calibration code in response to a voltage level of input data; and a plurality of main driving units configured to be selectively activated in response to an on-die termination code, wherein each main driving unit includes a plurality of first transistors and a plurality of second transistors having back bias terminals receiving the on-die termination code, wherein respective outputs of the plurality of main driving units are commonly connected to an output node, and wherein activated main driving units drive the output node in response to the pre-pull-up code or the pre-pull-down code.

2. The data output circuit according to claim 1 , wherein the calibration code and the on-die termination code are codes to compensate for impedance mismatch between a semiconductor memory apparatus and an external circuit, wherein the calibration code is a code which is generated by the semiconductor memory apparatus, and wherein the on-die termination code is a code which is provided from the external circuit.

3. The data output circuit according to claim 1 , wherein the pre-code generation unit generates the pre-pull-up code in response to the calibration code when a voltage level of the input data is at a high voltage level and the pre-code generation unit generates the pre-pull-down code in response to the calibration code when a voltage level of the input data is at a low voltage level.

4. The data output circuit according to claim 3 , wherein the pre-code generation unit comprises: a plurality of pre-pull-up code generating parts configured to drive respective bits of the calibration code and generate respective bits of the pre-pull-up code when the voltage level of the input data is at a high voltage level; and a plurality of pre-pull-down code generating parts configured to drive respective bits of the calibration code and generate respective bits of the pre-pull-down code when the voltage level of the input data is at a low voltage level.

5. The data output circuit according to claim 4 , wherein the pre-pull-up code generating parts lock the respective bits of the pre-pull-up code to a first specified voltage level when the voltage level of the input data is at a low voltage level, and wherein the pre-pull-down code generating parts lock the respective bits of the pre-pull-down code to a second specified voltage level when the voltage level of the input data is at high voltage level.

6. The data output circuit according to claim 1 , wherein each of the plurality of main driving units is inputted with one bit corresponding to the on-die termination code and is activated in response to the inputted bit.

7. The data output circuit according to claim 6 , wherein each of the plurality of main driving units comprises: a pull-up driving section configured to perform a pull-up operation for the output node in response to the pre-pull-up code; and a pull-down driving section configured to perform a pull-down operation for the output node in response to the pre-pull-down code.

8. The data output circuit according to claim 7 , wherein the pull-up driving section comprises the plurality of first transistors having gates which are respectively inputted with respective bits of the pre-pull-up code, sources which are applied with an operating voltage, and drains to which the output node is connected, and wherein the pull-down driving section comprises the plurality of second transistors having gates which are respectively inputted with respective bits of the pre-pull-down code, drains to which the output node is connected, and sources to which a ground terminal is connected.

9. The data output circuit according to claim 8 , wherein the plurality of first transistors have back bias terminals which are inputted with one bit corresponding to the on-die termination code, and wherein the plurality of second transistors have back bias terminals which are inputted with an inverted voltage level of the one bit inputted to the plurality of first transistors, whereby whether to activate the pull-up driving section and the pull-down driving section of each main driving unit is determined.

10. A data output circuit comprising: a pre-code generation unit configured to generate a pre-pull-up code and a pre-pull-down code in response to input data, an N code, and a P code; and a plurality of main driving units configured to be selectively activated in response to an on-die termination code, wherein each main driving unit includes transistors having back bias terminals receiving the on-die termination code, wherein respective outputs of the plurality of main driving units drive an output node, and wherein the pre-pull-up code and the pre-pull-down code determine a driving force of activated main driving units.

11. The data output circuit according to claim 10 , wherein the pre-code generation unit generates the pre-pull-up code according to the P code or the pre-pull-down code according to the N code in response to a voltage level of the input data.

12. The data output circuit according to claim 11 , wherein the N code includes first and second N code bits, the P code includes first and second P code bits, the pre-pull-up code includes first and second pre-pull-up code bits, and the pre-pull-down code includes first and second pre-pull-down code bits.

13. The data output circuit according to claim 12 , wherein the pre-code generation unit comprises: a first bit generating section configured to generate the first pre-pull-up code bit and the first pre-pull-down code bit in response to the input data, the first P code bit, and the first N code bit, and a second bit generating section configured to generate the second pre-pull-up code bit and the second pre-pull-down code bit in response to the input data, the second P code bit, and the second N code bit.

14. The data output circuit according to claim 13 , wherein the first bit generating section generates the first pre-pull-up code bit in response to the first P code bit when the voltage level of the input data is at a high voltage level, and generates the first pre-pull-down code bit in response to the first N code bit when the voltage level of the input data is at a low voltage level, and wherein the second bit generating section generates the second pre-pull-up code bit in response to the second P code bit when the voltage level of the input data is at a high voltage level, and generates the second pre-pull-down code bit in response to the second N code bit when the voltage level of the input data is at a low voltage level.

15. The data output circuit according to claim 14 , wherein the plurality of main driving units include first and second main driving units, wherein the on-die termination code includes first and second on-die termination code bits.

16. The data output circuit according to claim 15 , wherein the first main driving unit is activated in response to the first on-die termination code bit, and when activated, drives the output node in response to the first and second pre-pull-up code bits and the first and second pre-pull-down code bits, and wherein the second main driving unit is activated in response to the second on-die termination code bit, and when activated, drives the output node in response to the first and second pre-pull-up code bits and the first and second pre-pull-down code bits.

17. The data output circuit according to claim 16 , wherein the first main driving unit comprises: a first transistor having a gate which is inputted with the first pre-pull-up code bit, a source which is applied with an operating voltage, a drain to which the output node is connected and a back bias terminal to which the first on-die termination code bit is inputted; a second transistor having a gate which is inputted with the second pre-pull-up code bit, a source which is applied with the operating voltage, a drain to which the output node is connected and a back bias terminal to which the first on-die termination code bit is inputted; a third transistor having a gate which is inputted with the first pre-pull-down code bit, a drain to which the output node is connected, a source to which a ground terminal is connected and a back bias terminal to which an inverted signal of the first on-die termination code bit is inputted; and a fourth transistor having a gate which is inputted with the second pre-pull-down code bit, a drain to which the output node is connected, a source to which the ground terminal is connected and a back bias terminal to which the inverted signal of the first on-die termination code bit is inputted.

18. The data output circuit according to claim 16 , wherein the second main driving unit comprises: a first transistor having a gate which is inputted with the first pre-pull-up code bit, a source which is applied with the operating voltage, a drain to which the output node is connected and a back bias terminal to which the second on-die termination code bit is inputted; a second transistor having a gate which is inputted with the second pre-pull-up code bit, a source which is applied with the operating voltage, a drain to which the output node is connected and a back bias terminal to which the second on-die termination code bit is inputted; a third transistor having a gate which is inputted with the first pre-pull-down code bit, a drain to which the output node is connected, a source to which the ground terminal is connected and a back bias terminal to which an inverted signal of the second on-die termination code bit is inputted; and a fourth transistor having a gate which is inputted with the second pre-pull-down code bit, a drain to which the output node is connected, a source to which the ground terminal is connected and a back bias terminal to which the inverted signal of the second on-die termination code bit is inputted.