Data Processing System

1. An apparatus for processing data comprising: first processing circuitry configured to operate in a first power domain; second processing circuitry configured to operate in a second power domain different from said first power domain; shared processing circuitry configured to operate in a shared power domain such that said first processing circuitry and said shared processing circuitry are configurable to operate together to form a first hybrid processing unit having access to an external memory and said second processing circuitry and said shared processing circuitry are configurable to operate together to form a second hybrid processing unit having access to said external memory, wherein said first hybrid processing unit and said second hybrid processing unit together comprise a uni-processing environment for executing a single instruction stream; execution flow transfer circuitry configured to transfer execution of said single instruction stream between said first hybrid processing unit and said second hybrid processing unit at a transfer execution point, wherein said execution flow transfer comprises transfer of at least one bit of processing-state restoration information from a source one of said first hybrid processing unit and said second hybrid processing unit to a destination one of said first hybrid processing unit and said second hybrid processing unit, said processing-state restoration information being information enabling said destination hybrid processing unit to successfully resume execution of said single instruction stream from said transfer execution point; transmission circuitry configured to provide a transmission pathway from said source hybrid processing unit to said destination hybrid processing unit for said at least one bit of processing-state restoration information and wherein said transmission pathway bypasses said external memory, wherein the at least one bit of processing-state restoration information comprises at least one of: branch predictor history information, TLB contents, micro-TLB contents and data prefetcher pattern information; and power control circuitry configured to control said shared processing circuitry to operate at a first level of power consumption when said first hybrid processing unit has control of execution of said single instruction stream and to operate at a second different level of power consumption when said second hybrid processing unit has control of execution of said single instruction stream.

2. The apparatus as claimed in claim 1 , wherein said first processing circuitry and said second processing circuitry have different processing performance characteristics.

3. The apparatus as claimed in claim 2 , wherein said execution flow transfer circuitry comprises the power control circuitry for independently controlling power to said first processing circuitry and said second processing circuitry such that each of said first processing circuitry and said second processing circuitry can be placed in a powered-up state in which it is ready to perform processing operations and a power-saving state in which it is awaiting activation.

4. The apparatus as claimed in claim 3 , wherein said power control circuitry is configured to independently control power to said shared circuitry.

5. The apparatus as claimed in claim 3 , wherein said power control circuitry is configured to switch one of said first processing circuitry and said second processing circuitry corresponding to said destination hybrid processing unit from said power-saving state to said powered-up state and to switch the other of said first processing circuitry and said second processing circuitry corresponding to said source hybrid processing unit from said powered-up state to said power-saving state as part of said execution transfer process.

6. The apparatus as claimed in claim 2 , wherein said first processing circuitry and said second processing circuitry are architecturally compatible and wherein said first processing circuitry differs micro-architecturally from said second processing circuitry.

7. The apparatus as claimed in claim 6 , wherein said architectural compatibility comprises compatibility of at least one of general purpose registers, control registers and instruction sets.

8. The apparatus as claimed in claim 6 , wherein said micro-architectural differences between said first processing circuitry and said second processing circuitry comprise at least one of: pipeline length, instruction issue width, cache configuration, branch prediction capability and translation lookaside buffer (TLB) configuration.

9. The apparatus as claimed in claim 2 , wherein one of said first processing circuitry and said second processing circuitry is higher performance processing circuitry relative to the other of said first processing circuitry and said second processing circuitry and wherein said other of said first processing circuitry and said second processing circuitry is higher efficiency processing circuitry relative to said one of said first processing circuitry and said second processing circuitry.

10. The apparatus as claimed in claim 9 , wherein said apparatus is fabricated on a single integrated circuit with said higher performance processing circuitry being substantially physically localized to a first area of said integrated circuit and said higher efficiency processing circuitry being substantially physically localized to a second area of said integrated circuit and wherein said second area is different from said first area.

11. The apparatus as claimed in claim 2 , wherein said shared processing circuitry comprises cache circuitry.

12. The apparatus as claimed in claim 11 , wherein said shared cache circuitry comprises both level one cache circuitry and level two cache circuitry, each of said level one cache circuitry and said level two cache circuitry serving both higher performance processing circuitry and higher efficiency processing circuitry.

13. The apparatus as claimed in claim 11 , wherein said shared processing circuitry comprises translation lookaside buffer (TLB) circuitry.

14. The apparatus as claimed in claim 1 , comprising circuitry for stopping a clock signal to one of said first processing circuitry and said second processing circuitry that is not currently in control of execution of said single instruction stream.

15. The apparatus as claimed in claim 1 , wherein said shared processing circuitry comprises at least one of: cache circuitry, translation lookaside buffer circuitry, special purpose registers, bus interface circuitry, bus pins and trace circuitry.

16. The apparatus as claimed in claim 1 , wherein each of said first processing circuitry and said second processing circuitry comprises at least one of: a program counter, general purpose registers, branch prediction circuitry, decoding/sequencing circuitry, an execution datapath and load/store circuitry.

17. The apparatus as claimed in claim 1 , wherein said transmission pathway comprises a dedicated signal path between said first processing circuitry and said second processing circuitry.

18. The apparatus as claimed in claim 17 , wherein said transmission circuitry is configured to use a plurality of clock cycles to perform the transfer over said transmission pathway.

19. The apparatus as claimed in claim 1 , wherein said at least one bit of processing-state restoration information comprises at least one of: a program counter and at least a subset of general purpose register contents of said source hybrid processing unit at said transfer execution point.

20. The apparatus as claimed in claim 1 , wherein: at least said source hybrid processing unit comprises an associated non-shared cache as part of one of said first processing circuitry and said second processing circuitry corresponding to said source hybrid processing unit, said associated non-shared cache being separate from said shared processing circuitry.

21. The apparatus as claimed in claim 1 , wherein said execution flow transfer circuitry is configured to initiate said transfer of execution of said single instruction stream from said source hybrid processing unit to said destination hybrid processing unit in response to a hardware trigger such that said transfer is functionally transparent to an operating system and software executing on said data processing apparatus.

22. The apparatus as claimed in claim 21 , wherein said hardware trigger is at least one of: a temperature sensor, a series of cache misses, initiation of a hardware page table walk, processing circuitry entering a polling state and processing circuitry entering a wait-for-interrupt state.

23. The apparatus as claimed in claim 1 , wherein said execution flow transfer circuitry is configured to initiate said transfer of execution of said single instruction stream from said source hybrid processing unit to said destination hybrid processing unit in response to an external trigger.

24. The apparatus as claimed in claim 23 , wherein said external trigger is configured to receive a trigger stimulus from at least one of a temperature monitor and a power controller.

25. The apparatus as claimed in claim 1 , wherein said execution flow transfer circuitry is configured to initiate said transfer of execution of said single instruction stream from said source hybrid processing unit to said destination hybrid processing unit in response to a software trigger.

26. The apparatus as claimed in claim 25 , wherein said software trigger comprises a processor instruction.

27. The apparatus as claimed in claim 1 , comprising performance-level varying circuitry configured to vary a processing performance level of at least one of said first hybrid processing unit and said second hybrid processing unit.

28. The apparatus as claimed in claim 27 , wherein said performance-level varying circuitry is configured to perform dynamic voltage and frequency scaling of processing performance of at least one of said first hybrid processing unit and said second hybrid processing unit by varying at least one of: a voltage of said first power domain; a voltage of said second power domain; a voltage of said shared power domain; a frequency of operation of said first processing circuitry; a frequency of operation of said second processing circuitry and a frequency of operation of said shared processing circuitry.

29. A multi-processing data processing system comprising a plurality of uni-processing data processing apparatus and a bus providing a communication path between said plurality of uni-processing data processing apparatus, said multi-processing data processing system being configured to support concurrent execution a plurality of instruction streams in processing hardware, wherein said plurality of uni-processing data processing apparatus comprises at least one of the data processing apparatus as claimed in claim 1 .

30. An apparatus for processing data comprising: first processing circuitry configured to operate in a first power domain; second processing circuitry configured to operate in a second power domain different from said first power domain; shared processing circuitry configured to operate in a shared power domain such that said first processing circuitry and said shared processing circuitry are configurable to operate together to form a first hybrid processing unit having access to an external memory and said second processing circuitry and said shared processing circuitry are configurable to operate together to form a second hybrid processing unit having access to said external memory, wherein said first hybrid processing unit and said second hybrid processing unit together comprise a uni-processing environment for executing a single instruction stream; execution flow transfer circuit configured to transfer execution of said single instruction stream between said first hybrid processing unit and said second hybrid processing unit at a transfer execution point, wherein said execution flow transfer comprises transfer of at least one bit of processing-state restoration information from a source one of said first hybrid processing unit and said second hybrid processing unit to a destination one of said first hybrid processing unit and said second hybrid processing unit said processing-state restoration information being information enabling said destination hybrid processing unit to successfully resume execution of said single instruction stream from said transfer execution point: transmission circuitry configured to provide a transmission pathway from said source hybrid processing unit to said destination hybrid processing unit for said at least one bit of processing-state restoration information and wherein said transmission pathway bypasses said external memory, wherein the at least one bit of processing-state restoration information comprises at least one of: branch predictor history information TLB contents micro-TLB contents and data prefetcher pattern information, wherein said apparatus is fabricated on a single integrated circuit and wherein said shared power domain is configured to operate at a different voltage from voltages corresponding to each of said first power domain and said second power domain.

31. An apparatus for processing data comprising: first processing circuitry configured to operate in a first power domain; second processing circuitry configured to operate in a second power domain different from said first power domain; shared processing circuitry configured to operate in a shared power domain such that said first processing circuitry and said shared processing circuitry are configurable to operate together to form a first hybrid processing unit having access to an external memory and said second processing circuitry and said shared processing circuitry are configurable to operate together to form a second hybrid processing unit having access to said external memory, wherein said first hybrid processing unit and said second hybrid processing unit together comprise a uni-processing environment for executing a single instruction stream; execution flow transfer circuitry for transferring execution of said single instruction stream between said first hybrid processing unit and said second hybrid processing unit at a transfer execution point, wherein said execution flow transfer comprises transfer of at least one bit of processing-state restoration information from a source one of said first hybrid processing unit and said second hybrid processing unit to a destination one of said first hybrid processing unit and said second hybrid processing unit, said processing-state restoration information being information enabling said destination hybrid processing unit to successfully resume execution of said single instruction stream from said transfer execution point; wherein said first processing circuitry and said second processing circuitry have different processing performance characteristics; said shared processing circuitry comprises cache circuitry; and said shared cache circuitry is configured to serve as a level two cache for higher performance processing circuitry and configured to serve as a level one cache for higher efficiency processing circuitry.

32. An apparatus for processing data comprising: first processing circuitry configured to operate in a first power domain; second processing circuitry configured to operate in a second power domain different from said first power domain; shared processing circuitry configured to operate in a shared power domain such that said first processing circuitry and said shared processing circuitry are configurable to operate together to form a first hybrid processing unit having access to an external memory and said second processing circuitry and said shared processing circuitry are configurable to operate together to form a second hybrid processing unit having access to said external memory wherein said first hybrid processing unit and said second hybrid processing unit together comprise a uni-processing environment for executing a single instruction stream: execution flow transfer circuitry configured to transfer execution of said single instruction stream between said first hybrid processing unit and said second hybrid processing unit at a transfer execution point, wherein said execution flow transfer comprises transfer of at least one bit of processing-state restoration information from a source one of said first hybrid processing unit and said second hybrid processing unit to a destination one of said first hybrid processing unit and said second hybrid processing unit, said processing-state restoration information being information enabling said destination hybrid processing unit to successfully resume execution of said single instruction stream from said transfer execution point; and transmission circuit I configured to provide a transmission pathway from said source hybrid processing unit to said destination hybrid processing unit for said at least one bit of processing-state restoration information and wherein said transmission pathway bypasses said external memory, wherein the at least one bit of processing-state restoration information comprises at least one of: branch predictor history information, TLB contents, micro-TLB contents and data prefetcher pattern information, wherein said execution flow transfer circuitry is configured to initiate said transfer of execution of said single instruction stream from said source hybrid processing unit to said destination hybrid processing unit in response to a software trigger, wherein said software trigger comprises one of a write data access to a special purpose register and a write data access to a specific address in a memory map.

33. An apparatus for processing data comprising: first processing circuitry configured to operate in a first power domain; second processing circuitry configured to operate in a second power domain different from said first power domain; shared processing circuitry configured to operate in a shared power domain such that said first processing circuitry and said shared processing circuitry are configurable to operate together to form a first hybrid processing unit having access to an external memory and said second processing circuitry and said shared processing circuitry are configurable to operate together to form a second hybrid processing unit having access to said external memory, wherein said first hybrid processing unit and said second hybrid processing unit together comprise a uni-processing environment for executing a single instruction stream; execution flow transfer circuitry for transferring execution of said single instruction stream between said first hybrid processing unit and said second hybrid processing unit at a transfer execution point, wherein said execution flow transfer comprises transfer of at least one bit of processing-state restoration information from a source one of said first hybrid processing unit and said second hybrid processing unit to a destination one of said first hybrid processing unit and said second hybrid processing unit, said processing-state restoration information being information enabling said destination hybrid processing unit to successfully resume execution of said single instruction stream from said transfer execution point, wherein said execution flow transfer circuitry is configured to initiate said transfer of execution of said single instruction stream from said source hybrid processing unit to said destination hybrid processing unit in response to a software trigger; and virtualisation software running on said data processing apparatus provides said software trigger, said virtualisation software serving to mask configuration control information specific to said first processing circuitry and said second processing circuitry from an operating system executing on said data processing apparatus such that said transfer of execution of said single instruction stream is transparent to both an operating system and one or more applications executing on said data processing apparatus at a time corresponding to said transfer execution point, wherein one of said first processing circuitry and said second processing circuitry is higher performance processing circuitry relative to the other of said first processing circuitry and said second processing circuitry and wherein said other of said first processing circuitry and said second processing circuitry is higher efficiency processing circuitry relative to said one of said first processing circuitry and said second processing circuitry and wherein an exception or jump into said operating system or said virtualisation software from an application executing on said higher efficiency processing circuitry causes an automatic transfer of execution of said application to said higher performance processing circuitry.

34. An apparatus for processing data comprising: first means for processing configured to operate in a first power domain; second means for processing configured to operate in a second power domain different from said first power domain; means for shared processing configured to operate in a shared power domain such that said first means for processing and said means for shared processing are configurable to operate together to form a first means for hybrid processing having access to an external memory and said second means for processing and said means for shared processing are configurable to operate together to form a second means for hybrid processing having access to said external memory, wherein said first means for hybrid processing and said second means for hybrid processing together comprise a uni-processing environment for executing a single instruction stream; means for execution flow transfer for transferring execution of said single instruction stream between said first means for hybrid processing and said second means for hybrid processing at a transfer execution point, wherein said execution flow transfer comprises transfer of at least one bit of processing-state restoration information from a source one of said first means for hybrid processing and said second means for hybrid processing to a destination one of said first means for hybrid processing and said second means for hybrid processing, said processing-state restoration information being information enabling said destination means for hybrid processing to successfully resume execution of said single instruction stream from said transfer execution point; transmission means for providing a transmission pathway from said source hybrid processing unit to said destination hybrid processing unit for said at least one bit of processing-state restoration information and wherein said transmission pathway bypasses said external memory, wherein the at least one bit of processing-state restoration information comprises at least one of: branch predictor history information, TLB contents, micro-TLB contents and data prefetcher pattern information; and power control means for controlling said shared processing means to operate at a first level of power consumption when said first hybrid processing means has control of execution of said single instruction stream and to operate at a second different level of power consumption when said second hybrid processing means has control of execution of said single instruction stream.

35. A data processing method comprising the steps of: operating first processing circuitry in a first power domain; operating second processing circuitry in a second power domain different from said first power domain; operating shared processing circuitry in a shared power domain and forming a first hybrid processing unit by operating said first processing circuitry and said shared processing circuitry together, said first hybrid processing unit having access to an external memory; forming a second hybrid processing unit by operating said second processing circuitry and said shared processing circuitry together, said second hybrid processing unit having access to said external memory; providing a uni-processing environment for executing a single instruction stream, said uni-processing environment comprising said first hybrid processing unit and said second hybrid processing unit together; transferring execution of said single instruction stream between said first hybrid processing unit and said second hybrid processing unit at a transfer execution point using transfer execution circuitry, wherein said execution flow transfer comprises transfer of at least one bit of processing-state restoration information from a source one of said first hybrid processing unit and said second hybrid processing unit to a destination one of said first hybrid processing unit and said second hybrid processing unit, said processing-state restoration information being information enabling said destination hybrid processing unit to successfully resume execution of said single instruction stream from said transfer execution point; transmitting said at least one bit of processing-state restoration information via a transmission pathway from said source hybrid processing unit to said destination hybrid processing unit, wherein said transmission pathway bypasses said external memory, wherein the at least one bit of processing-state restoration information comprises at least one of: branch predictor history information, TLB contents, micro-TLB contents and data prefetcher pattern information; and controlling said shared processing circuitry to operate at a first level of power consumption when said first hybrid processing unit has control of execution of said single instruction stream and to operate at a second different level of power consumption when said second hybrid processing unit has control of execution of said single instruction stream.