Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory device system, comprising: a plurality of memory device die coupled to each other via a first plurality of through silicon vias, wherein the plurality of memory device die are stacked on top of each other and each of the memory device die contain a plurality of memory cells; a logic die coupled to the memory device dice through a second plurality of through silicon vias through which signals are coupled to and/or from each of the memory device dice, the logic die being operable to write data to and read data from the memory device dice, the logic die including an error checking system, comprising: an error code generator coupled to receive data written to at least one of the memory device die, the error code generator being operable to generate and store an error checking code corresponding to data to be written to an address in at least one of the memory device die, the error code generator further being operable to receive data read from an address in at least one of the memory device die and to generate an error checking code corresponding thereto; an error comparator coupled to receive the stored error checking code corresponding to data written to a read address in at least one of the memory device die and the generated error checking code corresponding to the data read from the read address in at least one of the memory device die, the error comparator being operable to indicate an error if a stored error checking code corresponding to the data read from the read address does not match the error code generated corresponding to the received data; and an embedded processor or hardware state machine configured to configured to examine addresses from which data was read that resulted in an error being indicated to detect an error pattern indicative of a faulty through silicon via of the first or second plurality of through silicon vias to which the logic die applies an address bit.
2. The memory device system of claim 1 wherein the error code generator is further operable responsive to the error indication to correct the data read from the read address in at least one of the memory device die and to cause the corrected read data to be rewritten to the read address.
3. The memory device system of claim 2 wherein the embedded processor or hardware state machine is configured to determine if the error indication was responsive to a hard error by first causing the corrected read data to be written to the read address and then causing the data thereafter stored at the read address to be read, and wherein the error checking system is operable to compare a stored error checking code generated from the corrected read data with an error checking code generated from the data thereafter stored at the read address, the embedded processor or hardware state machine further being operable to indicate a hard error responsive to receiving an error indication as a result of the comparison.
4. The memory device system of claim 1 wherein the memory device die are divided into a plurality of vaults each of which comprises corresponding sets of addresses of the plurality of memory device die.
5. The memory device system of claim 4 wherein the logic die further comprises: a plurality of downstream paths through which write commands, read commands, addresses and write data are coupled; a plurality of upstream paths through which read data are coupled; and an access circuit operable to couple each of the downstream paths to any of the vaults in the memory device die, and being operable to couple any of the vaults in the memory device die to each of the upstream paths.
6. The memory device system of claim 1 wherein the logic die further comprises an embedded processor or hardware state machine coupled to the error checking system, the embedded processor or hardware state machine being operable responsive to the error indication to redirect memory requests to the address from which the data was read that resulted in the error indication to a different address.
7. A memory device system comprising: a plurality of memory device die coupled to each other via a first plurality of through silicon vias, wherein the plurality of memory device die are stacked on top of each other and each of the memory device die contain a plurality of memory cells; a logic die coupled to the memory device dice through a second plurality of through silicon vias through which signals are coupled to and/or from each of the memory device dice, the logic die being operable to write data to and read data from the memory device dice, the logic die including an error checking system, comprising: an error code generator coupled to receive data written to at least one of the memory device die, the error code generator being operable to generate and store an error checking code corresponding to data to be written to an address in at least one of the memory device die, the error code generator further being operable to receive data read from an address in at least one of the memory device die and to generate an error checking code corresponding thereto; an error comparator coupled to receive the stored error checking code corresponding to data written to a read address in at least one of the memory device die and the generated error checking code corresponding to the data read from the read address in at least one of the memory device die, the error comparator being operable to indicate an error if a stored error checking code corresponding to the data read from the read address does not match the error code generated corresponding to the received data; and an embedded processor or hardware state machine configured to examine the data was read that resulted in an error being indicated to detect an error pattern indicative of a faulty through silicon via of the first or second plurality of through silicon vias to which the logic die applies a bit of write data or the memory die applies a bit of read data.
8. A system, comprising: a processor; a plurality of memory device die coupled to each other via a first plurality of through silicon vias, wherein the plurality of memory device die are stacked on top of each other and each of the memory device die contain a plurality of memory cells; and a logic die coupled to the processor and coupled to the memory device dice through a second plurality of through silicon vias vias through which signals are coupled to and/or from each of the memory device dice, the logic die being operable to write data to and read data from the memory device dice, the logic die including an error checking system, comprising: an error code generator coupled to receive data written to at least one of the memory device die, the error code generator being operable to generate and store an error checking code corresponding to data to be written to an address in at least one of the memory device die, the error code generator further being operable to receive data read from an address in at least one of the memory device die and to generate an error checking code corresponding thereto; an error comparator coupled to receive the stored error checking code corresponding to data written to a read address in at least one of the memory device die and the generated error checking code corresponding to the data read from the read address in at least one of the memory device die, the error comparator being operable to indicate an error if a stored error checking code does not match the generated error checking code; a memory access device coupled to the logic circuit die, the memory access device receiving the error indication from the logic circuit dice and being operable to apply memory requests to at least one of the memory device die, the memory access device further being operable in response to receiving the error indication from the logic circuit die to record the address corresponding to the memory cell being read that resulted in the error checking code being generated, the memory access device further being operable to thereafter issue memory requests to the at least one memory device die at addresses other than the recorded addresses; and an embedded processor or hardware state machine configured to examine signals received from the memory device die to detect an error pattern indicative of a faulty through silicon via of the first or second plurality of through silicon vias to which the logic die receives signals from the memory device dice.
9. The system of claim 8 wherein the embedded processor or hardware state machine is configured to determine if the error indication was generated responsive to a hard error by first generating a write command causing corrected read data to be written to the read address in at least one of the memory device die and to then generate a read command causing the corrected read data that was written to the read address in at least one of the memory device die to be read, and wherein the error comparator is operable to compare the stored error checking code generated from the corrected read data with the error checking code generated from the read corrected read data, the embedded processor or hardware state machine further being operable to generate and output a signal indicating a hard error responsive to receiving the error indication from the error comparator as a result of the comparison.
10. The system of claim 8 wherein the error code generator is operable to provide a request to the processor to suspend sending memory request to the logic die responsive to the embedded processor or hardware state machine detecting an error pattern indicative of a faulty through silicon via, and wherein the processor is operable to suspend sending memory requests to the logic die responsive to receiving the request from the logic die.
11. The system of claim 8 wherein the embedded processor or hardware state machine is further operable to examine the error pattern indicative of a faulty through silicon via and determine whether the faulty through silicon via is a through silicon via to which the logic die applies address signals to the memory device dice or a through silicon via through which data signals are coupled between the logic die and the memory device dice.
12. The system of claim 11 wherein the embedded processor or hardware state machine is further operable responsive to determining that the faulty through silicon via is a through silicon via to which the logic die applies address signals to the memory device dice to direct memory requests containing address signals that would be coupled through the faulty through silicon via to an address that does not require address signals to be coupled through the faulty through silicon via.
13. The system of claim 11 wherein the embedded processor or hardware state machine is further operable responsive to determining that the faulty through silicon via is a through silicon via through which data signals are coupled between the logic die and the memory device dice to mask the data bit that would be coupled through the faulty through silicon via.
14. The system of claim 8 wherein each of the memory device die comprise a respective dynamic random access memory device dice.
15. The system of claim 8 wherein the memory access device is operable to record the addresses corresponding to the memory cell being read that resulted in each of a plurality of error indications along with an indication of the time when the error occurred.
16. A method of writing data to and reading data from a plurality of memory device die connected to each other and to a logic die, wherein the plurality of memory device die are stacked on to of each other, the method comprising: writing data to an address in at least one of the plurality of memory device die stacked on top of each other by coupling write data to the logic die, wherein plurality of memory device die are coupled to each other via a plurality of through silicon vias, wherein the memory device dice are further coupled to the logic die by the plurality of through silicon vias of the plurality of through silicon vias through which signals are coupled to and/or from each of the memory device dice; generating an error checking code corresponding to the data written to the address in the at least one of the memory device die; storing the generated error checking code; subsequently reading data read from the address in the at least one of the memory device die; generating an error checking code corresponding to the data subsequently read from the address in the at least one of the memory device die; comparing the stored error checking code to the generated error checking code; in the event the stored error checking code does not match the generated error checking code, identifying the address from which the subsequently read data was read; thereafter writing data to and reading data from addresses in the at least one memory device die other than the identified address; and examining a plurality of bits of the identified address to detect an error pattern indicative of a fault through silicon via to which the logic die applies address signals to the memory device dice.
17. The method of claim 16 , further comprising redirecting memory requests to the identified address to a different address.
18. The method of claim 16 wherein the act of identifying the address from which the subsequently read data was read comprises: writing the corrected data to the address from which the data had been subsequently read; generating an error checking code corresponding to the corrected data; storing the generated error checking code corresponding to the corrected data; subsequently reading the corrected data at the address from which the data had been subsequently read; generating an error checking code corresponding to the subsequently read corrected data; comparing the stored error checking code corresponding to the corrected data to the generated error checking code corresponding to the subsequently read corrected data; and in the event the stored error checking code corresponding to the corrected data does not match the generated error checking code corresponding to the subsequently read corrected data, identifying the address from which the subsequently read corrected data was read.
19. The method of claim 16 wherein the act of identifying the address from which the subsequently read data was read comprises: in response to the stored error checking code not matching the error checking code corresponding to the subsequently read data, conducting a plurality of tests in the at least one memory device die at the address from which the subsequently read data was read; determining if the at least one memory die has failed a plurality of the tests; and in response to determining that the at least one memory die has failed a plurality of the tests, identifying the address from which the subsequently read data was read.
20. The method of claim 16 further comprising directing memory requests containing address signals that would be applied to the faulty through silicon via to which the logic die applies address signals to the memory device dice to an address that does not require address signals to be coupled through the faulty through silicon via.
21. A method of writing data to and reading data from a plurality of memory device die connected to each other and to a logic die, wherein the plurality of memory device die are stacked on top of each other, the method comprising: writing data to an address in at least one of the plurality of memory device die stacked on top of each other by coupling write data to the logic die, wherein plurality of memory device die are coupled to each other via a plurality of through silicon vias, wherein the memory device dice are further coupled to the logic die by the plurality of through silicon vias through which signals are coupled to and/or from each of the memory device dice; generating an error checking code corresponding to the data written to the address in the at least one of the memory device die; storing the generated error checking code; subsequently reading data read from the address in the at least one of the memory device die; generating an error checking code corresponding to the data subsequently read from the address in the at least one of the memory device die; comparing the stored error checking code to the generated error checking code; in the event the stored error checking code does not match the generated error checking code, identifying the address from which the subsequently read data was read; thereafter writing data to and reading data from addresses in the at least one memory device die other than the identified address; and examining data read from a plurality of identified addresses to detect an error pattern indicative of a faulty through silicon via of the plurality of through silicon vias through which data signals are coupled between the logic die and the memory device dice.
22. The method of claim 21 further comprising masking the data bit that would be coupled through the faulty through silicon via.
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June 17, 2014
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