Waveform Based Variational Static Timing Analysis

1. A method for statically analyzing timing of an electronic circuit design, the method comprising: characterizing substantially all circuit cells of a cell library to determine output waveform change information responsive to variations in one or more circuit parameters; in response to the characterizing, generating a time varying linear input model for each input and a time varying linear output model for each output of each logic gate of the integrated circuit; receiving a model for each linear interconnection network coupled between an output of a logic gate and an input of another logic gate; for each stage of the electronic circuit design, combining the time varying linear input model, the model for the respective linear interconnection network, and the time varying linear output model together into a set of matrix equations representative of the combined models; and solving, by using a processor, at each time step the set of matrix equations to determine an output waveform for each output of each stage of the electronic circuit design to efficiently simulate the electronic circuit design.

2. The method of claim 1 , further comprising: pushing an input waveform at an input to the electronic circuit design through one or more logic gate stages to an output of the electronic circuit design to determine an output waveform at the output of the electronic circuit design.

3. The method of claim 2 , further comprising: determining a time delay between an input waveform and the output waveform to perform a static timing analysis of the integrated circuit design.

4. The method of claim 3 , further comprising: determining a timing slew in the output waveform.

5. The method of claim 3 , wherein the time varying linear input model for each input and the time varying linear output model for each output of each logic gate are Norton equivalent circuit models including a time varying current, a time varying capacitance, and a time varying conductance.

6. The method of claim 1 , further comprising: pre-characterizing a range of behavior of logic gates in the electronic circuit by using a perturbation analysis of charge-current circuit equations.

7. The method of claim 6 , wherein pre-characterization comprises functional representation of a state vector (x) as a function of small variations in a circuit parameter (λ); wherein the state vector (x) is comprised of voltage at capacitive nodes and current through resistive nodes in the circuit.

8. The method of claim 1 , further comprising: prior to solving the set of matrix equations, applying a Schur transform to simplify the set of matrix equations; and solving the set of matrix equations using a Galerkin method to determine a compressed representation of each output waveform for each output of each stage of the electronic circuit design to efficiently simulate the electronic circuit design.

9. The method of claim 8 , wherein the solving of the set of matrix equations includes generating a set of possible output waveforms for each logic gate of the integrated circuit design; performing a singular value decomposition on the set of possible output waveforms to generate eigenvectors and eigenvalues; and comparing the eigenvalues with a predetermined threshold to determine the most significant eigenvalues to select their respective eigenvectors as the basis vectors.