Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A method of operation a system-on-chip (SoC) including a master block and a slave block, which communicate with each other through a bus, the method comprising: storing real-time information indicating whether the master block is a real-time block in a real-time information register of the master block; storing a weight information in a weight register of the master block based on the real-time information; checking buffer information of the master block; generating a quality-of-service (QoS) signal using the buffer information and the weight information; and determining a priority of the master block for using the bus based on the QoS signal.
A system-on-chip (SoC) prioritizes bus access for different components. Each "master block" (like a CPU or GPU) stores whether it needs real-time access in its own register. It also stores a "weight" value, based on its real-time needs, in another register. The block checks how full its data buffer is. Using the buffer level and the weight, it creates a "quality-of-service" (QoS) signal. This QoS signal determines how important this block is to get access to the bus. The higher the QoS signal, the higher the priority for using the bus.
2. The method of claim 1 , further comprising determining a priority of the master block for accessing the slave block based on the QoS signal.
The SoC from the previous description not only prioritizes bus access, but also prioritizes access to a specific "slave block" (like memory or a peripheral). The "quality-of-service" (QoS) signal, calculated based on the master block's buffer level and real-time needs, is used to determine which master block gets access to the slave block. The higher the QoS, the higher the priority to access the slave block.
3. The method of claim 2 , wherein the determining the priority of the master block for using the bus comprises: sending a bus use request signal comprising the QoS signal from the master block to a bus arbiter; and permitting, by the bus arbiter, the master block to use the bus over another master block having a lower priority based on the QoS signal provided to the bus arbiter as part of a request signal.
In the SoC, prioritizing bus access uses a bus arbiter. The master block sends a "bus use request" signal that includes its calculated "quality-of-service" (QoS) signal to the arbiter. The bus arbiter then compares the QoS signals from different master blocks. If one master block has a higher QoS signal (meaning it's more urgent), the arbiter allows it to use the bus, even if another master block requested it earlier. The higher the QoS, the higher the priority.
4. The method of claim 2 , wherein the determining the priority of the master block to access the slave block comprises: sending a slave access request signal comprising the QoS signal from the master block to the slave block; and permitting, by the slave block, the master block having higher priority than the other master block to access the slave block based on the QoS signal provided to the slave block as part of a slave access request signal.
In the SoC, prioritizing access to a "slave block" involves the master block sending a "slave access request" to that slave block, including the "quality-of-service" (QoS) signal. The slave block (like memory) then uses the QoS signal to decide which master block gets access first. A master block with a higher QoS signal gets priority over other master blocks requesting the same slave block, granting access based on need.
5. The method of claim 4 , wherein the slave block comprises a memory scheduler configured to schedule an access to a memory.
In the SoC described previously, the slave block that is being accessed is a memory scheduler. This memory scheduler is responsible for coordinating access to a memory resource, ensuring that the master block with the highest priority, as determined by the "quality-of-service" (QoS) signal, gets scheduled for memory access. The memory scheduler manages and organizes memory access requests.
6. The method of claim 1 , wherein the QoS signal has a linear, non-linear or piece-linear relation with the buffer information.
In the SoC, the relationship between the "quality-of-service" (QoS) signal and the buffer information can vary. It can be a direct, linear relationship (QoS increases proportionally with buffer level). It can be a non-linear relationship (QoS changes in a more complex way with buffer level). Or, it can be a "piece-linear" relationship, where the relationship is linear within certain ranges of buffer levels, but changes slope at different thresholds.
7. A method of operation a system-on-chip (SoC) including a master block and a slave block, which communicate with each other through a bus, the method comprising: storing a look-up table comprising a plurality of quality-of-service (QoS) signals in the master block; checking buffer information of the master block; fetching a QoS signal corresponding to the buffer information from the look-up table; and determining a priority of the master block to use the bus based on the QoS signal.
The system-on-chip (SoC) prioritizes bus access by using lookup tables. Each "master block" stores a table that maps buffer information to "quality-of-service" (QoS) signals. The master block checks its buffer level. It then looks up the corresponding QoS signal in the table. The QoS signal determines the priority for bus access. Higher QoS signals mean higher priority for the master block to use the bus.
8. The method of claim 7 , wherein the look-up table is changed according to an operation mode of the master block.
In the SoC with lookup tables, the specific lookup table used to determine the "quality-of-service" (QoS) signal can change depending on how the master block is currently operating. Different modes of operation (e.g., high-performance, low-power) can use different tables, allowing the system to dynamically adjust priority based on the master block's current needs. The lookup table content can be changed according to operation mode.
9. The method of claim 8 , further comprising selecting a look-up table from among a plurality of look-up tables according to the operation mode of the master block when the plurality of look-up tables are provided.
In the SoC, if multiple lookup tables are provided for the master block, the system selects one of these tables based on the current operation mode of the master block. For example, a high-performance mode might use a lookup table that prioritizes low-latency access, while a low-power mode might use a table that prioritizes energy efficiency. The selected lookup table defines how buffer information maps to a "quality-of-service" (QoS) signal.
10. The method of claim 8 , further comprising generating and storing the look-up table according to the operation mode of the master block.
The system-on-chip (SoC) generates and stores the lookup table based on the current operation mode of the master block. Instead of pre-defined tables, the system dynamically creates a table tailored to the specific requirements of the operation mode. This table maps the master block's buffer information to a "quality-of-service" (QoS) signal, enabling adaptive priority management.
11. The method of claim 7 , further comprising determining a priority of the master block to access the slave block based on the QoS signal.
Like before, in the SoC prioritizing bus access with lookup tables, it ALSO uses the "quality-of-service" (QoS) signal to determine the priority of a "master block" when accessing a "slave block" (like memory). The QoS signal, derived from the lookup table based on buffer information, is used to decide which master block gets access to the slave block first. This ensures consistent prioritization across both bus and slave block access.
12. The method of claim 11 , wherein the determining of the priority of the master block to use the bus comprises: sending a bus use request signal comprising the QoS signal from the master block to a bus arbiter; and permitting, by the bus arbiter, the master block to use the bus over another master block having a lower priority based on the QoS signal provided to the bus arbiter as part of the bus use request signal.
In this lookup table SoC, the master block sends a "bus use request" signal, including its "quality-of-service" (QoS) signal, to a bus arbiter. The bus arbiter uses the QoS signal to prioritize bus access. If one master block sends a higher QoS signal, the arbiter allows it to use the bus, even if another master block requested the bus earlier. The QoS signal sent as part of the bus use request grants access.
13. The method of claim 11 , wherein the determining the priority of the master block to access the slave block comprises: sending a slave access request signal comprising the QoS signal from the master block to the slave block; and permitting, by the slave block, the master block having higher priority than the other master block to access the slave block based on the QoS signal provided to the slave block as part of the slave access request signal.
In the SoC using lookup tables, prioritizing access to a "slave block" works by sending a "slave access request" including the "quality-of-service" (QoS) signal to the slave block. The slave block (like memory) uses the QoS signal to decide which master block gets access first. A higher QoS signal means higher priority to access the slave block over other requests.
14. The method of claim 13 , wherein the slave block comprises a memory scheduler configured to schedule an access to a memory.
The slave block being accessed, using lookup tables, is a memory scheduler that handles access requests to a memory resource. The scheduler uses the "quality-of-service" (QoS) signal from each master block to determine the order in which memory access requests are granted, giving priority to blocks with higher QoS values.
15. A system-on-chip comprising: a plurality of master blocks; a slave block; and a bus configured to carry communications signals between the plurality of master blocks and the slave block, wherein each of the plurality of master blocks comprises: a buffer configured to store data to be transmitted to or received from the bus; and a quality-of-service (QoS) generator configured to retrieve information of the buffer and generate a QoS signal using the retrieved buffer information, wherein the bus comprises a bus arbiter configured to determine a priority of each of the plurality of master blocks to use the bus based on the QoS signal of each of the plurality of master blocks, and wherein the QoS signal of each of the plurality of master blocks has a value set according to an operation modes of each of the plurality of master blocks.
A system-on-chip (SoC) contains multiple "master blocks" (like CPUs or GPUs) and a "slave block" (like memory), connected by a bus. Each master block has a data buffer and a "quality-of-service" (QoS) generator. The QoS generator looks at the buffer level and creates a QoS signal. The bus includes a bus arbiter. The arbiter uses the QoS signals from all master blocks to decide which block gets to use the bus first. The QoS signal depends on the operation mode of each master block.
16. The system-on-chip of claim 15 , wherein each of the plurality of master blocks further comprises: a real-time information register configured to store real-time information indicating whether each of the plurality of master blocks is a real-time block; and a weight register configured to store a weight of each of the plurality of master blocks based on the real-time information, and wherein the QoS generator generates the QoS signal using the buffer information and the weight.
In the SoC described, each master block contains a real-time information register storing whether the block needs real-time access, and a weight register storing a weight value based on this real-time flag. The "quality-of-service" (QoS) generator calculates the QoS signal using both the buffer information and the weight. This allows real-time blocks to get higher priority based on their urgency.
17. The system-on-chip of claim 15 , wherein the QoS generator comprises a plurality of look-up tables each of which comprises a plurality of QoS entries, the QoS generator selects one of the look-up tables based on the operation mode of the master block, and the QoS generator fetches a QoS entry corresponding to the buffer information from the selected look-up table.
In the SoC architecture described, the "quality-of-service" (QoS) generator contains several lookup tables, each containing QoS entries. The QoS generator selects one of these lookup tables based on the master block's operation mode. Then, it retrieves a QoS entry corresponding to the current buffer information from the selected table, and uses that value as the QoS signal for bus arbitration.
18. The system-on-chip of claim 15 , wherein the QoS generator generates and stores a look-up table according to the operation mode of the master block and fetches QoS information corresponding to the buffer information from the look-up table.
The QoS generator calculates and saves a lookup table based on the master block's operation mode. Then it retrieves QoS information corresponding to the buffer information from the dynamically generated lookup table, which grants access to the memory based on the current parameters.
19. The system-on-chip of claim 15 , wherein the slave block determines a priority of each of the plurality of master block to access the slave block based on the QoS signal.
In the SoC, the slave block determines the access priority for master blocks using the "quality-of-service" (QoS) signals. This means that in addition to the bus arbiter using QoS to control bus access, the slave block itself (like memory) also considers the QoS signal when deciding which master block to serve first.
20. The system-on-chip of claim 15 , wherein the slave block comprises a memory scheduler configured to schedule an access to a memory.
In the described SoC, the slave block is a memory scheduler, which schedules memory access. The memory scheduler uses the "quality-of-service" (QoS) signal generated by each master block to prioritize memory access requests. Master blocks with higher QoS signals get preferential access to the memory.
21. A method of operation a system-on-chip (SoC), comprising: storing real-time information indicating whether a first master block is a real-time block in a first register of the first master block; storing real-time information indicating whether a second master block is a real-time block in a first register of the second master block; storing weight information for the first master block in a second register of the first master block based on the real-time information indicating whether the first master block is a real-time block; storing weight information for the second master block in a second register of the second master block based on the real-time information indicating whether the second master block is a real-time block; checking buffer information of the first and second master blocks; generating a quality-of-service (QoS) signal for the first master block using the buffer information and the weight information for the first master block; generating a quality-of-service (QoS) signal for the second master block using the buffer information and the weight information for the second master block; and determining a relative priority of the first and second master blocks for using the bus based on the generated QoS signals for the first and second master block.
In a system-on-chip (SoC), two master blocks need bus access. Each block has a register that indicates if it requires real-time access. Each block also has a weight register storing a weight based on its real-time status. The system checks the buffer levels of both blocks. For each block, a "quality-of-service" (QoS) signal is generated based on its buffer level and weight. The QoS signals are compared to determine the relative priority of the two blocks for using the bus.
22. An electronic system comprising: a system-on-chip (SoC); and a non-volatile memory configured to store data used by the SoC, wherein the SoC comprises: a plurality of master blocks; a slave block; and a bus configured to carry communications signals between the plurality of master blocks and the slave block, wherein each of the plurality of master blocks comprises: a buffer configured to store data to be transmitted to or received from the bus; and a quality-of-service (QoS) generator configured to retrieve information of the buffer and generate a QoS signal using the retrieved buffer information, wherein the bus comprises a bus arbiter configured to determine a priority of each of the plurality of master blocks to use the bus based on the QoS signal of each of the plurality of master blocks, and wherein the QoS signal of each of the plurality of master blocks has a value set according to an operation modes of each of the plurality of master blocks.
An electronic system consists of a system-on-chip (SoC) and a non-volatile memory that stores data for the SoC. The SoC contains multiple "master blocks" (like CPUs or GPUs) and a "slave block" (like memory), connected by a bus. Each master block has a data buffer and a "quality-of-service" (QoS) generator. The QoS generator looks at the buffer level and creates a QoS signal. The bus includes a bus arbiter. The arbiter uses the QoS signals from all master blocks to decide which block gets to use the bus first, and the QoS signal depends on the operation mode of each master block.
Unknown
July 29, 2014
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.