Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An apparatus, comprising: an arbitration unit coupled to a plurality of request queues for a target circuit, wherein each request queue is configured to store requests generated by a respective one of a plurality of master circuits, wherein a request queue of one of the plurality of master circuits includes one or more queue stages, wherein each queue stage is configured to store a request from the master circuit and is associated with a respective latch, wherein the master circuit is configured to send, via the one or more respective latches, an indication specifying that a request has been submitted; wherein the one or more latches are driven separately from latches implementing the one or more queue stages such that the arbitration unit is configured to receive the sent indication while the request associated with the indication has stalled in one of the one or more queue stages; wherein the arbitration unit is configured to arbitrate between requests in the plurality of request queues based on information indicative of an ordering in which requests were submitted to the plurality of request queues by the plurality of master circuits, wherein the information includes the received indication, and wherein the arbitration unit is configured to determine when the request was submitted based on the received indication.
An apparatus arbitrates requests from multiple master circuits to a target circuit. Each master has a request queue with stages (like a mini-FIFO) that stores its requests. Importantly, there's a separate mechanism using latches (memory elements) for each master to signal that a request has been sent. These latches are independent from the request queue's latches, meaning the arbitration unit can receive the "request submitted" signal even if the actual request is stuck (stalled) in the queue. The arbitration unit prioritizes requests based on the order in which they were submitted, using these signals to determine the original submission order.
2. The apparatus of claim 1 , wherein each of the plurality of master circuits are configured to submit, with each request to the target circuit, an indication specifying that a request has been submitted, and wherein the arbitration unit is configured to determine the ordering in which requests were submitted based on the submitted indications.
The apparatus has multiple master circuits that, when sending a request to a target circuit, also send an indication specifying that the request was submitted. An arbitration unit determines the order in which requests were submitted based on these submitted indications. This contrasts with systems where the ordering is inferred only from the arrival time of the request itself, which can be affected by variable latencies. This independent indication allows for a more accurate arbitration.
3. The apparatus of claim 2 , wherein the indications further specify a priority for a respective request, and wherein the arbitration unit is configured to select between a plurality of requests received at the same time based on the specified priorities.
The apparatus described above, where master circuits send submission indications, extends the indication to include a priority level for the request. The arbitration unit then uses these priorities to select between requests received at the same time. So, if multiple requests arrive concurrently, the arbitration unit will service the request with the highest priority as indicated in the submission signal.
4. An apparatus, comprising: a master circuit configured to send a request to a target circuit and an indication of the request via a plurality of latch stages, wherein the plurality of latch stages includes a first set of latches configured to store the request as the request is sent to the target circuit, wherein the plurality of latches includes a second set of latches configured to store the indication, wherein the second set of latches are driven separately from the first set of latches; wherein the target circuit is configured to receive requests from a plurality of master circuits, and wherein the apparatus is configured to determine, based on the sent indication, an order in which the target circuit is to service ones of the received requests; and wherein the master circuit is configured to send requests to a plurality of target circuits and a plurality of indications, each indicating that a respective one of the requests has been submitted, and wherein the master circuit is configured to process responses for each of the requests in only the ordering in which the master circuit sent the requests.
An apparatus features a master circuit that sends a request to a target circuit *and* a separate "request submitted" indication. The request and indication travel through separate sets of latches. The target circuit receives requests from multiple masters, and the overall system determines the order to service these requests based on the sent indications. Critically, the master circuit only processes responses to its requests in the *exact* order it sent them, ensuring correct data handling even if the target circuit services requests out of order due to arbitration. The master can send requests and indications to multiple target circuits.
5. The apparatus of claim 4 , wherein the master circuit is configured to send the requests along one of a plurality of paths to a respective one of the plurality of target circuits, and wherein each of the plurality of paths has the same number of latch stages.
The apparatus described above, where a master circuit sends requests and indications to multiple target circuits, does so along different paths. Each path from the master to a target circuit has the *same* number of latch stages. This path length matching aims to equalize latency, so indication timing is reliable across different target circuits for fair arbitration.
6. The apparatus of claim 4 , wherein the master circuit is configured to send the indication of the request to an arbitration unit associated with the target circuit, wherein the arbitration unit is configured to determine the ordering based on indications sent by ones of the plurality of master circuits.
The apparatus described above, where a master sends a request and an indication, transmits the "request submitted" indication to an arbitration unit associated with the target circuit. This arbitration unit determines the request servicing order based on indications received from *all* the master circuits. The arbitration unit centralizes arbitration decisions.
7. The apparatus of claim 4 , wherein the first set of latches is configured to implement a first-in-first-out (FIFO) queue, wherein the apparatus is configured to drive the first set of latches in response to a request being removed from the FIFO queue by the target circuit, and wherein the apparatus is configured to drive the second set of latches during each clock cycle.
The apparatus described above uses a FIFO queue for the requests. The latches of this FIFO are driven when a request is removed by the target circuit. The latches sending the indication are driven every clock cycle. This ensures the signal of the request is sent as soon as possible, even when the request itself is stuck in the FIFO.
8. An apparatus, comprising: a target circuit configured to receive requests from a respective one of a plurality of request queues, where each of the requests was generated by a respective one of a plurality of master circuits; wherein the target circuit is configured to service the requests in an ordering specified by an arbitration unit, wherein the arbitration unit is configured to determine the ordering based on information provided by the plurality of master circuits indicative of when requests were submitted to the plurality of request queues; and wherein the target circuit is configured to respond to a received request by sending a burst response to a master circuit that generated the request.
An apparatus comprises a target circuit that receives requests from multiple request queues, each originating from a different master circuit. The target circuit services these requests in an order determined by an arbitration unit. Crucially, the arbitration unit bases its ordering decision on information *provided by the master circuits* that indicates when the requests were submitted to the queues. The target circuit then responds to a received request by sending a "burst response" (multiple data units) back to the originating master circuit.
9. The apparatus of claim 8 , wherein each request queue is associated with a set of latches, and wherein a master circuit is configured to write, in response to submitting a request to one of the plurality of request queues, a value to the set of latches associated with that request queue.
The apparatus described above, with the target circuit receiving requests from multiple queues, has each queue associated with its own set of latches. When a master circuit submits a request to a queue, it also writes a value to the latches associated with *that* queue. This value acts as the "request submitted" indication.
10. The apparatus of claim 9 , wherein the set of latches are configured to propagate the value to the arbitration unit when the submitted request stalls in the request queue, and wherein the arbitration unit is configured to determine that a request has been submitted to the request queue based on receiving the value.
The apparatus described above, where a value is written to latches upon request submission, uses these latches to propagate the value to the arbitration unit when the submitted request *stalls* in the queue. The arbitration unit infers that a request has been submitted to the queue based on receiving this value. This addresses situations where requests may experience variable delays within the queue.
11. The apparatus of claim 8 , further comprising: a plurality of target circuits including the target circuit, wherein each target circuit is configured to receive requests from a respective plurality of request queues, wherein each queue in a respective plurality of request queues has the same length, and wherein queues in different ones of the pluralities of request queues have different lengths.
The apparatus contains multiple target circuits, each receiving requests from multiple request queues. Within *each* target circuit's set of queues, the queues are the *same* length. However, queues connecting to *different* target circuits can have *different* lengths. This allows for flexibility in system design where some target circuits might require longer buffering.
12. An apparatus, comprising: a first set of latches configured to implement stages of a request queue for a target circuit, wherein the first set of latches is configured to propagate a request generated by a master circuit to the target circuit; a second set of latches configured to propagate an identifier from the master circuit to an arbitration unit, wherein the identifier indicates that a request has been submitted, wherein the arbitration unit is configured to determine an ordering in which the target circuit is to service requests received from a plurality of master circuits based on identifiers received from the plurality of master circuits, and wherein the second set of latches are configured to be latched separately from the first set of latches; and a third set of latches configured to implement stages of a response queue for the target circuit, wherein the third set of latches are configured to propagate a response for a request from the target circuit to the master circuit.
An apparatus arbitrates requests to a target circuit with three sets of latches: a first set implementing the request queue for forwarding requests to the target, a second set forwarding an "identifier" from the master to the arbitration unit to signify a request has been sent, and a third set for the response queue. The arbitration unit orders requests based on the identifiers received from multiple masters, while the identifier latches are controlled *independently* from the request queue latches.
13. The apparatus of claim 12 , wherein the propagated identifier is a single bit that is written by the master circuit upon submitting a request to the first set of latches, and wherein the arbitration unit is configured to determine when a request has been submitted to the first set of latches based on when the arbitration unit received the single bit.
In the apparatus described above with separate latches, the "identifier" propagated by the second set of latches is a *single bit*. The master circuit sets this bit when submitting a request to the queue. The arbitration unit then determines that a request has been submitted based on when it receives this single bit. This simplifies the signaling mechanism.
14. The apparatus of claim 12 , wherein the propagated identifier is a value that is written by the master circuit upon submitting a request to the first set of latches, wherein the arbitration unit is configured to determine when a request has been submitted to the first set of latches and a priority of the request based on the received value.
In the apparatus described above with separate latches, the propagated "identifier" is a *value* written by the master circuit when submitting a request. The arbitration unit uses this value to determine *both* when a request was submitted *and* the request's priority.
15. The apparatus of claim 12 , wherein the apparatus is configured to provide a first set of latch signals to the first set of latches to cause the first set of latches to propagate a request from the master circuit to the target circuit, and to provide a second latch signal to cause the second set of latches to propagate an identifier from the master circuit to the arbitration unit, and wherein the apparatus is configured to cycle the second signal when the apparatus is not cycling the first set of signals.
In the apparatus above with the first set of latches for a request queue and a second set of latches for the indication, the first set uses a latch signal to propagate the request. A second signal is used for the indication. The apparatus cycles the signal for the indication even when it isn't cycling the signal for the request queue. This means that the indication is consistently sent, irrespective of what happens with the queue.
16. A method, comprising: a master circuit submitting a request to one of a plurality of request queues for a target circuit and an indication of the request to an arbitration unit, wherein the request queue includes a first plurality of latches configured to propagate the request from the master circuit to the target circuit, and wherein the master circuit submits the indication via a second set of latches to the arbitration unit; latching the second set of latches separately from latching the first set of latches; the arbitration unit determining that the request was submitted to the request queue based on the submitted indication; and based on the determining, the arbitration unit selecting an ordering in which the target circuit is to service requests from the plurality of requests queues.
A method involves a master circuit submitting a request to a queue for a target circuit *and* sending an indication of that request to an arbitration unit via separate latches. The latches sending the indication are controlled separately. The arbitration unit detects the request based on this indication and then determines the order in which to service requests from the different queues.
17. The method of claim 16 , wherein the arbitration unit receives the indication of the request while the request is stalled in the request queue and waiting to be serviced by the target circuit.
In the method of submitting a request and an indication, the arbitration unit receives the indication even while the request is *stalled* in the queue, waiting to be processed by the target circuit. This is because the indication signal is sent through separate latches.
18. The method of claim 16 , wherein the indication is a single bit written by the master circuit to the second set of latches.
In the method of submitting a request and an indication, the indication is a *single bit* written by the master circuit to the separate set of latches. The simplicity of just sending a single bit reduces overhead.
19. The method of claim 16 , wherein the plurality of request queues includes a first queue having a first number of stages and a second queue having a second number of stages, wherein the first number of stages is different than the second number of stages.
In the method of submitting a request and an indication, the request queues can have different lengths. One queue might have a different number of stages than another queue. This heterogeneity enables better resource allocation.
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July 29, 2014
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