Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A method of maintaining coherency in a memory subsystem of an electronic system having hardware and software components modeled in a first design abstraction in a software simulator and a second design abstraction in a hardware emulator in electrical communication with the software simulator during functional verification of the electronic system, wherein a portion of the memory subsystem has a plurality of memory pages modeled in the software simulator using the first design abstraction, wherein a first flag is associated with each memory page of the plurality of memory pages, wherein a shadow memory page is modeled in the hardware emulator using the second design abstraction to store a copy of a contents of a memory page of the plurality of memory pages, and wherein a second flag is associated with the shadow memory page and is to be set to indicate that the memory page is more recently updated than the shadow memory page, comprising: updating the memory page modeled in the first design abstraction in the software simulator by writing data to at least a portion of the memory page; setting the first flag associated with the memory page to indicate that the memory page in the software simulator is more recently updated than the shadow memory page in the hardware emulator; setting the second flag associated with the shadow memory page to indicate that the memory page is more recently updated than the shadow memory page; receiving a request to access the shadow memory page from a portion of the circuit design programmed into the hardware emulator; checking whether the second flag is set after a request to access the shadow memory page is received; writing the contents of the memory page in the software simulator to the shadow memory page in the hardware emulator prior to granting the request to access the shadow memory page; and clearing the first flag and the second flag.
A method for keeping memory consistent between a software simulator and a hardware emulator during chip design verification. The simulator uses a first, higher-level model, and the emulator uses a second, lower-level model of the hardware. A portion of the memory being verified is mirrored between the simulator and emulator using "shadow memory". When the simulator updates a memory page, a flag is set to indicate the simulator's version is newer. Before the emulator accesses its shadow copy, it checks this flag. If the flag is set, the simulator's memory page is copied to the emulator's shadow memory, and the flag is cleared, ensuring the emulator always has the most up-to-date data.
2. The method of claim 1 , wherein a third flag is associated with each memory page of the plurality of memory pages, and wherein a fourth flag is associated with the shadow memory page, further comprising: updating the shadow memory page modeled in the second design abstraction by writing data to at least a portion of shadow the memory page; setting the third flag associated with the memory page to indicate that the shadow memory page is more recently updated than the memory page; setting the fourth flag associated with the shadow memory page to indicate that the shadow memory page is more recently updated than the memory page; receiving a request to access the memory page from a portion of the circuit design; checking whether the second flag is set after a request to access the shadow memory page is received; writing the contents of the memory page to the shadow memory page prior to granting the request to access; and clearing the third flag and the fourth flag.
A method extending the memory coherency process where updates can happen in either the software simulator or the hardware emulator. If the hardware emulator updates its shadow memory page, a flag is set to indicate its version is newer. Before the simulator accesses its original memory page, it checks this flag. If set, the emulator's shadow memory page content is copied to the simulator's memory page and the flags are cleared. This ensures both sides always have the latest version regardless of which side last wrote to the memory. This requires two flags for each side, one to signal updates from the software simulator and another to signal updates from the hardware emulator.
3. The method of claim 1 , wherein the first design abstraction is a SystemC abstraction, and wherein the second design abstraction is a register transfer level abstraction.
This is a specific implementation of the memory coherency method where the software simulator uses SystemC for its design abstraction and the hardware emulator uses Register Transfer Level (RTL). SystemC models hardware at a higher level of abstraction than RTL, so this claim specifies that SystemC is used in the software simulator and RTL in the hardware emulator to keep them coherent.
4. The method of claim 3 , further comprising setting a flag of a flag array to prevent writing the contents of the memory page to the shadow memory page.
An extension to the memory coherency method where a flag is used to temporarily disable the copying of data from the simulator's memory page to the emulator's shadow memory page. This "do not copy" flag, part of a larger flag array, provides a mechanism to prevent unnecessary or unwanted data transfers between the simulator and emulator, possibly for debugging or optimization purposes, while still performing coherency checks.
5. The method of claim 1 , further comprising: observing a performance metric of the memory subsystem for various memory page and shadow memory page sizes; generating a profile of memory synchronization events; and calculating an optimized memory page and shadow memory page size.
The memory coherency method also includes performance analysis. The system monitors how quickly memory is accessed and synchronized between the simulator and emulator for different memory page sizes. It then generates a profile of these synchronization events and calculates the optimal memory page size to improve the overall performance of memory operations during verification.
6. The method of claim 1 , wherein writing the contents of the memory page is performed in a single API call per block transfer.
A feature of the memory coherency method is that data transfer between the simulator and emulator memory happens using a single API call for each block of data transferred. This means that a large amount of data can be copied from one memory to another with a single instruction, optimizing bandwidth.
7. A method of maintaining coherency in a memory subsystem of an electronic system having hardware and software components modeled in a first design abstraction in a software simulator and a second design abstraction in a hardware emulator in electrical communication with the software simulator during functional verification of the electronic system, wherein a portion of the memory subsystem has a plurality of memory pages modeled in the software simulator using the first design abstraction, wherein a first flag is associated with each memory page of the plurality of memory pages, wherein a shadow memory page is modeled in the hardware emulator using the second design abstraction to store a copy of a contents of a memory page of the plurality of memory pages, and wherein a second flag is associated with the shadow memory page and is to be set to indicate that the memory page is more recently updated than the shadow memory page, comprising: writing data to at least a portion of the memory page modeled in the first design abstraction in the software simulator; detecting that the data has been written; queuing an event to update the second flag associated with the shadow memory page in the hardware emulator; queuing an event to write a contents of the memory page modeled in the software simulator to the shadow memory page modeled in the hardware emulator; setting the second flag to indicate that the memory page is more recently updated than the shadow memory page; writing the contents of the memory page to the shadow memory page prior to granting a request to access the shadow memory page; and clearing the second flag.
A method for maintaining memory consistency between a software simulator and a hardware emulator, but with asynchronous updates. When data is written to a memory page in the simulator, the system detects this write and queues two events. The first event updates the flag associated with the shadow memory in the emulator. The second event copies the data from the simulator's memory page to the shadow memory in the emulator. The flag is set, and the data is copied. Before the emulator accesses the shadow memory, it's guaranteed to have the most recent data due to the queued events. The flag is then cleared after the copy.
8. The method of claim 7 , wherein the first design abstraction is a SystemC abstraction, and wherein the second design abstraction is a register transfer level abstraction.
The asynchronous memory coherency method from claim 7 uses SystemC in the software simulator and RTL in the hardware emulator.
9. The method of claim 8 , wherein queuing the event to write a contents of the memory page to the shadow memory page comprises queuing the event to the command and control space of the register transfer level abstraction.
A refinement of the asynchronous memory coherency process (from claim 7) where the event to copy the data from the simulator to the emulator is sent to the command and control space of the RTL emulator. This means that the copy operation is managed and scheduled by the emulator's control system, allowing for potentially complex interactions with other emulator operations.
10. The method of claim 7 , wherein the first design abstraction is a register transfer level abstraction, and wherein the second design abstraction is a SystemC abstraction.
This asynchronous memory coherency method (from claim 7) uses RTL in the software simulator and SystemC in the hardware emulator, the reverse of Claim 8.
11. The method of claim 10 , wherein queuing the event to write a contents of the memory page to the shadow memory page comprises queuing a CPU interrupt to write a contents of the shadow memory page.
The asynchronous memory coherency method, using RTL in the software simulator and SystemC in the hardware emulator (as in Claim 10), triggers a CPU interrupt to write the data. This leverages the CPU interrupt mechanism to handle the data transfer to the shadow memory page.
12. The method of claim 10 , further comprising setting a flag of a flag array to prevent writing the contents of the memory page to the shadow memory page.
A feature of the asynchronous memory coherency method (from claim 10) is that a flag prevents writing the contents of the memory page to the shadow memory page.
13. The method of claim 7 , further comprising: observing a performance metric of the memory subsystem for various memory page and shadow memory page sizes; generating a profile of memory synchronization events; and calculating an optimized memory page and shadow memory page size.
The asynchronous memory coherency method (from claim 7) also includes performance analysis where the system observes performance metrics, generates profiles of memory synchronization events, and calculates optimized sizes for memory and shadow memory pages.
14. A computer-readable non-transitory storage medium having stored thereon a plurality of instructions, the plurality of instructions when executed by a computer, cause the computer to perform: providing a memory subsystem of an electronic system having hardware and software components modeled in a first design abstraction and a second design abstraction during functional verification of the electronic system, wherein a portion of the memory subsystem is modeled in the first design abstraction having a plurality of memory pages, and wherein a shadow memory page is modeled in the second design abstraction to store a copy of a contents of a memory page of the plurality of memory pages; updating the memory page modeled in a first design abstraction by writing data to at least a portion of the memory page; setting a first flag associated with the memory page to indicate that the memory page is more recently updated than the shadow memory page, wherein the first flag is associated with each memory page of the plurality of memory pages; setting a second flag associated with the shadow memory page to indicate that the memory page is more recently updated than the shadow memory page, wherein the second flag is associated with the shadow memory page and is to be set to indicate that the memory page is more recently updated than the shadow memory page; receiving a request to access the shadow memory page from a portion of the circuit design; checking whether the second flag is set after a request to access the shadow memory page is received; writing the contents of the memory page to the shadow memory page prior to granting the request to access the shadow memory page; and clearing the first flag and the second flag.
A computer-readable storage medium storing instructions to perform memory coherency between a software simulator and a hardware emulator. The instructions cause the computer to mirror memory pages between the simulator and emulator, use flags to track which copy is more up-to-date, copy data from the simulator to the emulator when the emulator's copy is stale and a request to access said copy is received, and clear the flags after the copy.
15. The computer-readable non-transitory storage medium of claim 14 , the plurality of instructions when executed by a computer, cause the computer to further perform: updating the shadow memory page modeled in the second design abstraction by writing data to at least a portion of shadow the memory page; setting a third flag associated with the memory page to indicate that the shadow memory page is more recently updated than the memory page, wherein the third flag is associated with each memory page of the plurality of memory pages; setting a fourth flag associated with the shadow memory page to indicate that the shadow memory page is more recently updated than the memory page, wherein the fourth flag is associated with the shadow memory page; receiving a request to access the memory page from a portion of the circuit design; checking whether the second flag is set after a request to access the shadow memory page is received; writing the contents of the memory page to the shadow memory page prior to granting the request to access; and clearing the third flag and the fourth flag.
A computer-readable storage medium (building upon the instructions from Claim 14) that also allows updates to originate from the hardware emulator. It includes instructions to update flags and copy data from the emulator to the simulator when the simulator's copy of the memory is stale and access is requested, ensuring two-way coherency between the two systems.
16. The computer-readable non-transitory storage medium of claim 14 , wherein the first design abstraction is a SystemC abstraction, and wherein the second design abstraction is a register transfer level abstraction.
A computer-readable storage medium (from Claim 14) where the software simulator uses SystemC and the hardware emulator uses RTL for their design abstractions.
17. The computer-readable non-transitory storage medium of claim 14 , the plurality of instructions when executed by a computer, cause the computer to further perform setting a flag of a flag array to prevent writing the contents of the memory page to the shadow memory page.
A computer-readable storage medium (from Claim 14) that includes instructions for setting a flag to prevent writing the contents of a memory page to the shadow memory page.
18. The computer-readable non-transitory storage medium of claim 14 , the plurality of instructions when executed by a computer, cause the computer to further perform: observing a performance metric of the memory subsystem for various memory page and shadow memory page sizes; generating a profile of memory synchronization events; and calculating an optimized memory page and shadow memory page size.
A computer-readable storage medium (from Claim 14) storing instructions that perform performance analysis of the memory subsystem by observing metrics, generating profiles, and calculating optimized sizes for the memory pages.
19. The computer-readable non-transitory storage medium of claim 14 , wherein writing the contents of the memory page is performed in a single API call per block transfer.
A computer-readable storage medium (from Claim 14) where the memory page data transfer occurs via a single API call per block transfer.
20. A computer-readable non-transitory storage medium having stored thereon a plurality of instructions, the plurality of instructions when executed by a computer, cause the computer to perform: providing a memory subsystem of an electronic system having hardware and software components modeled in a first design abstraction and a second design abstraction during functional verification of the electronic system, wherein a portion of the memory subsystem is modeled in the first design abstraction having a plurality of memory pages, wherein a first flag is associated with each memory page of the plurality of memory pages, and wherein a shadow memory page is modeled in the second design abstraction to store a copy of a contents of a memory page of the plurality of memory pages; writing data to at least a portion of the memory page modeled in the first design abstraction; detecting that the data has been written; queuing an event to update a second flag associated with the shadow memory page, wherein the second flag is associated with the shadow memory page and is to be set to indicate that the memory page is more recently updated than the shadow memory page; queuing an event to write a contents of the memory page to the shadow memory page; setting the second flag to indicate that the memory page is more recently updated than the shadow memory page; and writing the contents of the memory page to the shadow memory page prior to granting a request to access the shadow memory page; and clearing the second flag.
A computer-readable storage medium containing instructions for asynchronous memory coherency. When a memory page in the software simulator is updated, the system detects this, queues events to update a flag in the hardware emulator and to copy the data. The flag indicates the simulator is up-to-date, and the copy ensures the emulator has the latest data. This is done before the emulator accesses the data and then the flag is cleared.
21. The computer-readable non-transitory storage medium of claim 20 , wherein the first design abstraction is a SystemC abstraction, and wherein the second design abstraction is a register transfer level abstraction.
A computer-readable storage medium (from Claim 20) where the software simulator uses SystemC and the hardware emulator uses RTL for their design abstractions.
22. The computer-readable non-transitory storage medium of claim 21 , wherein queuing the event to write a contents of the memory page to the shadow memory page comprises queuing the event to the command and control space of the register transfer level abstraction.
A computer-readable storage medium (from Claim 21) where the queued event to copy memory to the shadow memory page is sent to the command and control space of the RTL emulator.
23. The computer-readable non-transitory storage medium of claim 20 , wherein the first design abstraction is a register transfer level abstraction, and wherein the second design abstraction is a SystemC abstraction.
A computer-readable storage medium (from Claim 20) using RTL in the software simulator and SystemC in the hardware emulator.
24. The computer-readable non-transitory storage medium of claim 23 , wherein queuing the event to write a contents of the memory page to the shadow memory page comprises queuing a CPU interrupt to write a contents of the shadow memory page.
A computer-readable storage medium (from Claim 23) that queues a CPU interrupt to write the contents of the shadow memory page.
25. The computer-readable non-transitory storage medium of claim 20 , the plurality of instructions when executed by a computer, cause the computer to further perform setting a flag of a flag array to prevent writing the contents of the memory page to the shadow memory page.
A computer-readable storage medium (from Claim 20) that sets a flag to prevent writing the contents of the memory page to the shadow memory page.
26. The computer-readable non-transitory storage medium of claim 20 , the plurality of instructions when executed by a computer, cause the computer to further perform: observing a performance metric of the memory subsystem for various memory page and shadow memory page sizes; generating a profile of memory synchronization events; and calculating an optimized memory page and shadow memory page size.
A computer-readable storage medium (from Claim 20) that performs performance analysis for different sizes.
27. A functional verification system for verifying a circuit design modeled in a plurality of abstractions while maintaining memory coherency, comprising: a software simulator programmed with a model of a first portion of a circuit design in a first design abstraction, including a first portion of a memory subsystem that comprises a memory page of a memory page pair and a first flag associated with the memory page; and a hardware emulator programmed with a model of a second portion of a circuit design in a second design abstraction, including a second portion of the memory subsystem that comprises a shadow memory page of the memory page pair and a second flag associated with the shadow memory page, wherein the hardware emulator is electrically connected to the software simulator to allow communication during functional verification; wherein the first flag when set indicates that the memory page is more recently updated than the shadow memory page, and is configured to be set in response to a write access to the memory page, and wherein the second flag when set indicates that the memory page is more recently updated than the shadow memory page, and is configured to be set to prevent a request to access the shadow memory page in response to a write access to the memory page, and cleared to allow the request to access the shadow memory page after a contents of the memory page is copied to the shadow memory page.
A system for verifying a circuit design using both a software simulator and a hardware emulator while ensuring memory consistency. The simulator models part of the design, including a memory page and a flag. The emulator models another part, including a shadow memory page and its flag. When the simulator updates its memory page, its flag is set. This flag prevents the emulator from accessing the shadow copy until the data has been copied from the simulator to the emulator. Once copied, the flag is cleared, allowing access.
28. The functional verification system of claim 27 , wherein the model of the memory subsystem further comprises: a third flag, associated with the second memory page, to indicate when set that the second memory page is more recently updated than the first memory page, wherein the third flag is configured to be set in response to a write access to the second memory page; and a fourth flag, associated with the first memory page, to indicate when set that the second memory page is more recently updated than the first memory page, wherein the fourth flag is configured to be set in response to a write access to the second memory page and cleared after a contents of the second memory page is copied to the first memory page.
In addition to the functional verification system from Claim 27, updates can also be made in the hardware emulator. A third flag indicates when the emulator's shadow memory page is more up-to-date than the simulator's memory page. A fourth flag on the simulator's side prevents accesses until the emulator data has been copied into it. These additional flags and data transfers create a symmetric system where either side can make updates.
29. The functional verification system of claim 27 , wherein the first design abstraction is a SystemC abstraction, and wherein the second design abstraction is a register transfer level abstraction.
The functional verification system of claim 27 is set up such that the software simulator uses SystemC and the hardware emulator uses RTL.
30. The functional verification system of claim 27 , wherein the second portion of the memory subsystem further comprises a flag array, including the second flag, to prevent writing the contents of the first memory page to the second memory page.
The functional verification system from Claim 27 includes a flag array in the emulator which includes flags that prevent writing the contents of memory from the software simulator to the hardware emulator.
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July 29, 2014
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