Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A method comprising: (a) generating a layout of an integrated circuit (IC) design using an electronic design automation (EDA) tool, the layout having a network of routing paths connecting at least two active layer devices of the IC design; (b) computing estimated parasitic capacitances of the routing paths of the network; (c) performing a first device level simulation of the network based on the at least two active layer devices and the estimated parasitic capacitances; (d) using the EDA tool to revise the layout or a device of the IC design if a result of the first device level simulation fails to satisfy an IC specification; wherein steps (b), (c) and (d) are performed one or more times before performing design rule checks and before performing layout-versus-schematic checks, until a result of the first device level simulation satisfies the IC specification; and (e) outputting the revised layout of the IC design to a non-transitory, machine readable storage medium after completion of steps (b) to (d), to be accessed by the EDA tool to perform design verification.
This method uses electronic design automation (EDA) software to create a layout for an integrated circuit (IC). The layout includes wiring that connects active devices. The method then estimates parasitic capacitances (unwanted capacitance) in the wiring. A device-level simulation checks the circuit's performance based on the active devices and these estimated capacitances. If the simulation fails to meet IC specifications, the EDA software revises either the layout or a device. The estimation, simulation, and revision steps repeat until the specifications are met, BEFORE running design rule checks and layout-versus-schematic checks. Finally, the revised layout is saved for later verification.
2. The method of claim 1 , wherein the first device level simulation is a pre-layout simulation based on active layer devices, the pre-layout simulation excluding interconnect routings except for the estimated parasitic capacitance of step (b).
This method refines the device-level simulation from the previous claim. Specifically, the simulation is a "pre-layout" simulation. This means it primarily focuses on the active devices themselves. It ignores the detailed wiring, EXCEPT that the simulation does include the estimated parasitic capacitance values calculated earlier, as if they were components directly connected to the devices. Essentially, the simulation accounts for wiring capacitance without fully modeling the wiring layout.
3. The method of claim 1 , further comprising: automatically comparing the estimated parasitic capacitances of the routing paths of the network to respective predetermined values; and providing a notification if one of the predetermined values is exceeded.
Building upon the first method, this adds an automatic check for the estimated parasitic capacitances. It compares each estimated capacitance value in the wiring to a pre-defined acceptable limit. If any estimated capacitance exceeds its limit, the system provides a notification, potentially alerting the designer to a problem before more detailed simulations are run. This allows earlier detection of potential performance issues.
4. A method comprising: providing a previously verified integrated circuit (IC) design implemented at a first technology node and having routing paths, the IC design to be ported to a second technology node being different from the first technology node; using an electronic design automation (EDA) tool to compute estimated parasitic capacitances of the routing paths of the previously verified IC design using a technology file associated with the second technology node; and estimating parasitic capacitances using a shrink factor based on the first and second technology nodes, wherein the step of using the EDA tool to compute estimated parasitic capacitances includes: accessing a table stored in a non-transitory, machine readable storage medium, the table containing a plurality of previously computed parasitic capacitance values corresponding to respective combinations of line length, line width and line spacing.
This method deals with porting an existing, verified IC design to a newer technology. The design, originally made using a first technology, is adapted for a second technology. The method uses EDA software to estimate parasitic capacitances in the circuit's wiring, but using technology files specific to the *second* technology. It also uses a "shrink factor," based on the size difference between the two technologies, to adjust the estimated capacitances. The EDA software accesses a table of pre-calculated capacitance values (indexed by wire length, width, and spacing) to perform these estimations.
5. The method of claim 4 , further comprising: performing design rule checks, layout-versus-schematic checks, layout parameter extraction and RC extraction of the IC design at the second technology node using the EDA tool, where the step of performing design rule checks is not performed for the IC design at the second technology node until after the resizing step is completed.
This method extends the technology porting process from the previous claim. It includes performing standard design rule checks, layout-versus-schematic checks, layout parameter extraction, and RC extraction using the EDA tool, BUT importantly, the design rule checks are NOT performed until after the earlier technology porting and resizing steps are completed. This ensures the design is initially adapted for the new technology before being thoroughly checked for manufacturing rule violations.
6. The method of claim 5 , further comprising: performing a post-layout simulation after the step of performing design rule checks.
This method adds a final post-layout simulation step to the technology porting process described in the previous claim. After design rule checks and other verifications are completed, a final simulation is run to confirm the performance of the ported design in the new technology, taking into account all extracted parasitic effects from the final layout.
7. The method of claim 4 , wherein the step of using the EDA tool to compute estimated parasitic capacitances further includes: interpolating between parasitic capacitance values in the table to compute parasitic capacitance coupling values for combinations of line length, line width and line spacing which are not included in the table.
In the technology porting method, the estimation of parasitic capacitances is improved. Instead of simply looking up values in the table of pre-calculated capacitances, the system *interpolates* between values. This means if the exact combination of wire length, width, and spacing isn't in the table, the system estimates the capacitance by averaging or otherwise calculating a value based on the nearest entries in the table, leading to a more accurate estimation.
8. The method of claim 4 , further comprising: causing a display device to display a portion of a layout containing the IC design.
This simply describes a user interface addition to the technology porting method. The system displays a portion of the IC layout on a screen, allowing a designer to visually inspect the design as it is being ported and resized.
9. The method of claim 4 , further comprising causing a display device to display a schematic of a portion of the IC design, with a symbol representing a lumped device having one of the parasitic capacitances.
Another user interface enhancement for the technology porting method. In addition to the layout, the system displays a schematic diagram of a portion of the IC. Critically, the schematic shows a capacitor symbol representing one of the calculated parasitic capacitances, giving the designer a visual representation of the parasitic effects being considered.
10. The method of claim 4 , wherein the shrink factor is a ratio of a critical dimension of the second technology node to a critical dimension of the first technology node.
This clarifies the definition of the "shrink factor" used in the technology porting method. The shrink factor is calculated as the ratio of a "critical dimension" (e.g., minimum feature size) in the second technology node divided by the corresponding critical dimension in the first technology node. This ratio is used to scale the physical dimensions and capacitances during the porting process.
11. A non-transitory, computer readable storage medium encoded with computer program instructions, such that when the computer program instructions are executed by a computer, the computer acts as a special purpose processor for performing a method comprising: (a) generating a layout of an integrated circuit (IC) design using an electronic design automation (EDA) tool, the layout having a network of routing paths connecting at least two active layer devices of the IC design; (b) computing estimated parasitic capacitances of the routing paths of the network; (c) performing a first device level simulation of the network based on the at least two active layer devices and the estimated parasitic capacitances; (d) using the EDA tool to revise the layout or a device of the IC design if a result of the first device level simulation fails to satisfy an IC specification; wherein steps (b), (c) and (d) are performed one or more times before performing design rule checks and before performing layout-versus-schematic checks, until a result of the first device level simulation satisfies the IC specification; and (e) outputting the revised layout of the IC design to a non-transitory, machine readable storage medium after completion of steps (b) to (d), to be accessed by the EDA tool to perform design verification.
This describes a computer-readable storage medium (e.g., a hard drive, flash drive) containing instructions that, when executed by a computer, cause the computer to perform the steps of the method described in the first claim: create an IC layout, estimate parasitic capacitances, perform a device-level simulation, revise the layout based on simulation results, repeating until the design meets specifications, and then output the revised layout. In essence, it's a software implementation of the first method.
12. The non-transitory, computer readable storage medium of claim 11 , wherein the first device level simulation is a pre-layout simulation based on active layer devices, the pre-layout simulation excluding interconnect routings except for the estimated parasitic capacitance of step (b).
This specifies that the computer program from the previous claim implements a pre-layout simulation as described in the second claim. This means the simulation focuses on the active devices themselves and includes the estimated parasitic capacitances, but excludes detailed interconnect routing.
13. The non-transitory, computer readable storage medium of claim 11 , further comprising: (f) performing design rule checks, layout-versus-schematic checks, layout parameter extraction and RC extraction of the IC design using the EDA tool, where step (f) is not performed for the IC design until after step (d) is completed.
This extends the computer program from the first claim to perform additional verification steps. It performs design rule checks, layout-versus-schematic checks, layout parameter extraction, and RC extraction. Importantly, these steps are performed *after* the iterative layout revision process based on parasitic estimation and device-level simulation is complete (step d from claim 11).
14. The non-transitory, computer readable storage medium of claim 11 , wherein step (b) includes: accessing a table stored in a non-transitory, machine readable storage medium, the table containing a plurality of previously computed parasitic capacitance values corresponding to respective combinations of line length, line width and line spacing.
This refines the computer program from the first claim by specifying how parasitic capacitances are calculated. Step (b) in claim 11, which computes estimated parasitic capacitances, involves accessing a table of pre-calculated values indexed by wire length, width, and spacing.
15. The non-transitory, computer readable storage medium of claim 14 , wherein step (b) further includes: interpolating between parasitic capacitance values in the table to compute parasitic capacitance coupling values for combinations of line length, line width and line spacing which are not included in the table.
The computer program from claim 14 performs capacitance estimation by interpolating between the parasitic capacitance values in the table to calculate parasitic capacitance coupling values for combinations of line length, line width, and line spacing which are not directly included in the table, as described in claim 7.
16. A system comprising: an electronic design automation (EDA) tool, for generating a schematic design of an integrated circuit (IC), generating a layout from the schematic design, editing the layout, and verifying the schematic design and layout; at least one non-transitory, computer readable storage medium, for storing data representing the schematic design and the layout, the layout having a network of routing paths connecting at least two active layer devices of the IC design; an RC tool for computing estimated parasitic capacitances of the routing paths of the network before verifying the schematic design and layout, and before performing design rule checks and before performing layout-versus-schematic checks, and for inserting a capacitor corresponding to the estimated parasitic capacitance into the data representing the schematic design of the IC; and a first device level simulation tool for simulating performance of the network based on the at least two active layer devices and the estimated parasitic capacitances.
This describes a system for IC design. It includes EDA software for creating, editing, and verifying IC designs. It also has storage to hold the design data. An RC tool estimates parasitic capacitances in the wiring *before* design verification steps such as DRC/LVS. The RC tool also adds capacitors to the schematic design to represent these parasitic capacitances. Finally, a simulation tool simulates the circuit's performance based on active devices and the estimated parasitic capacitances.
17. The system of claim 16 , wherein the first device level simulation tool is configured to perform a pre-layout simulation based on active layer devices and the inserted capacitor, the pre-layout simulation excluding interconnect routings.
This specifies that the device-level simulation tool in the system from the previous claim performs a "pre-layout" simulation. This simulation is based on active devices and the capacitors inserted to represent parasitic effects, but it excludes the detailed interconnect routing.
18. The system of claim 16 , wherein the EDA tool is configured for performing design rule checks, layout-versus-schematic checks, layout parameter extraction and RC extraction of the IC design, and the RC tool is configured for computing estimated parasitic capacitances for the network without using outputs of the design rule checks, layout-versus-schematic checks, layout parameter extraction and RC extraction of the IC design.
This expands on the description of the EDA tool in the system. It specifies that the EDA tool performs design rule checks, layout-versus-schematic checks, layout parameter extraction, and RC extraction. Critically, the RC tool estimates parasitic capacitances WITHOUT using the results of these later DRC/LVS/extraction steps. This indicates that the estimation is done early in the design flow to guide layout modifications.
19. The system of claim 16 , wherein the RC tool includes: a table stored in the at least one non-transitory, machine readable storage medium, the table containing a plurality of previously computed parasitic capacitance values corresponding to respective combinations of line length, line width and line spacing.
This provides more detail about the RC tool in the system. The RC tool uses a table stored in memory. This table contains pre-calculated parasitic capacitance values based on wire length, width, and spacing. This allows the RC tool to quickly estimate capacitance without complex calculations.
20. The system of claim 19 , wherein the RC tool is configured for interpolating between parasitic capacitance values in the table to compute parasitic capacitance coupling values for combinations of line length, line width and line spacing which are not included in the table.
This clarifies how the RC tool uses the capacitance table. The RC tool interpolates between the parasitic capacitance values in the table to compute parasitic capacitance coupling values for combinations of line length, line width, and line spacing that aren't explicitly in the table, as previously described.
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August 12, 2014
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